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Online Calibration of the D0 Vertex Detector
Initialization Procedure and
Database Usage
Harald FoxD0 Experiment
Northwestern University
Online Calibration of theD0 Vertex Detector
What is Online Calibration?
Determination of:– Threshold for zero-suppression of the read out.– Pedestals and gains for the Level 3 Trigger and the
Prompt Reconstruction.
When and Where?
• When?– Special calibration run between 2 machine
fillings.– The time window for calibration is negotiable
between D0, CDF, and the accelerator.– The Secondary Data Acquisition (SDAQ) is
foreseen for this task.
When and Where?
• Where?– The calibration process runs on the front end
processor of each readout crate.– Data is transferred to the CPU instead of the
Level 3 Trigger.– Pedestals and gains are calculated locally and
stored in the database.– New threshold values are calculated from
pedestals.
What?
• The D0 Silicon Tracker consists of 6 barrels, 12 F-disks, and 8 H-disks 800,000 channels.
• Commissioning and testing requires read out of a complete barrel (432 SVX, 55300 channels).
• Each SVX read out chip has its own parameters.
Database GUI Manipulation Monitoring
Calibration Steps
A. Start a calibration run (Taker/COOR).
B. Initialization of the electronics (“download”).
– The initialization is part of COMICS.
– An ORACLE database is used to store:• Download Parameters• History of time
dependent informationJune, 2000 T. Yasuda, Fermilab
Taker
COOR
COMICS
CratesCrates
CalibrationManager
CalibrationDatabase
Calib. DataProcessor
DatabaseInterface
Configure
Request start run
Request download
Download Start run
End run
Data
PedestalsGains
PedestalsGains
ComparisonResults
DatabaseAccess
End calib.
Start run, End run
Online CalibrationOnline CalibrationSystemSystem
Validator
Calib ManagerGUI
Calibration Steps (cont.)
C. Determine pedestals and gains (Huaming Wang).
– 5 Calibration voltages.
– Pedestals and gains Calibration Manager.
D. The Validator checks errors and consistency.
June, 2000 T. Yasuda, Fermilab
Taker
COOR
COMICS
CratesCrates
CalibrationManager
CalibrationDatabase
Calib. DataProcessor
DatabaseInterface
Configure
Request start run
Request download
Download Start run
End run
Data
PedestalsGains
PedestalsGains
ComparisonResults
DatabaseAccess
End calib.
Start run, End run
Online CalibrationOnline CalibrationSystemSystem
Validator
Calib ManagerGUI
Calibration Steps (cont.)
E. Calibration data Calibration Database.
F. New thresholds are calculated.
– Used for next initialization.
June, 2000 T. Yasuda, Fermilab
Taker
COOR
COMICS
CratesCrates
CalibrationManager
CalibrationDatabase
Calib. DataProcessor
DatabaseInterface
Configure
Request start run
Request download
Download Start run
End run
Data
PedestalsGains
PedestalsGains
ComparisonResults
DatabaseAccess
End calib.
Start run, End run
Online CalibrationOnline CalibrationSystemSystem
Validator
Calib ManagerGUI
Design of theElectronics Database
• The hardware is mirrored:– Crates, modules, module
channels, and silicon detectors.– Multiple to multiple connections
between modules are allowed.
• Download parameters are stored.
• The path from a VME Readout Board (VRB) to a silicon detector (HDI) is traceable.
• A history of all modifications is kept.
The Initialization Process
• The initialization is integrated in the online environment (COMICS).
• A Python (OO-scripting language) program is used for downloading.
• The program is partitioned into 3 layers:1. Hardware layer:
• Knows about module and register addresses.
• Communication via EPICS.
The Initialization Process (Program Layers)
2. The database layer:• The hardware configuration is determined in a
database lookup.
• Download parameters are extracted.
3. GUI for expert interaction:• Allows modification of the database.
• Manipulation of each hardware module.
• Status display.
Database Layer
• Each hardware module and database table is represented by an object.
• The database is accessed via an interface design pattern.
• This allows an optimization of the database access.
• The electronics configuration is determined on a crate to crate basis.
• Each module is initialized in the proper sequence.
GUI Layer
• The GUI is an interaction tool for the experts. It replaces a PC based support tool.
• It gives an overview for each crate allowing basic operations.
Used for the barrel read out right now.
GUI Layer (cont.)
GUI Layer (cont.)
• A detailed view allows interaction with all hardware modules. This allows the initialization of single modules or module chains.
• Allows modification of the database:– Enable/disable of modules for the subsequent download.
– Change of hardware configuration (re-cabling).
– Change of initialization parameters.
– Calculation of new thresholds.
Use Cases
Three test stands are available:
Northwestern 1% (SiDet) 10% (SiDet)
Complete Barrel
2 HDI 2 HDI 7 (72) HDI
2 VRB 1 VRB 5 (9) VRB
768 Channel 2304 Channel 4992 (55296) Channel
Milestone Goal Achieved!
• We successfully demonstrated the Online Calibration at the 10% test stand!
• The Silicon Tracker is the first detector using the complete Online Calibration System!
• Pedestals and gains were calculated and stored in the Online Database.
• Data was send to the Level 3 Trigger and saved to disk. SMT examine was used to monitor the data taking process.
Conclusion
• The D0 Silicon Tracker requires online calibration. Demanding task with 800,000 channels!
• We developed database and GUI tools necessary to meet the challenge.
• We developed the program running on the Front End Processor determining pedestals and gains.
• These tools were successfully tested in the D0 Online Calibration Framework.
We are leading the development.
Hardware Configuration
• VRB: VME Read Out Board
• SEQ: SVX Sequencer
Silicon Read-Out Data Flow
platformplatform
SEQ
SEQ
SEQ
SEQ
SEQ
SEQ
VRB Controller
Optical Link1Gb/s
3/6/8/9 Chip HDI
Sensor
V
B
D
V
R
B
V
R
B
V
R
B
V
R
B
68k Bit3
PC
Silicon Graphics
L3MPM
VME
Low Mass 3M
1553
NRZ / CLK
HV / LV
Hardware Configuration
• VRB: VME Read Out Board
• SEQ: SVX Sequencer
Silicon Read-Out Data Flow
platformplatform
SEQ
SEQ
SEQ
SEQ
SEQ
SEQ
VRB Controller
Optical Link1Gb/s
3/6/8/9 Chip HDI
Sensor
V
B
D
V
R
B
V
R
B
V
R
B
V
R
B
68k Bit3
PC
Silicon Graphics
L3MPM
VME
Low Mass 3M
1553
NRZ / CLK
HV / LV
UML Diagram of the Database Layer
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