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Newspaper Vending Machine Controller Design Specification
Consider a newspaper vending machine like those found at many street corners. Newspapers cost 35 cents, and the machine accepts nickels, dimes and quarters. When enough money has been deposited, the machine unlocks a door which allows the buyer to retrieve a newspaper, and returns change if necessary. You will design the control logic for this vending machine as a finite-state machine using D flip-flops. The coin slot mechanism detects which coin has been deposited, and produces two signals A and B that represent the value of the coin as shown in the table below. Invalid coins are pennies, foreign currency, etc., and are immediately returned to the buyer.
Coin A BNo coin deposited, or invalid coin 0 0 Nickel 0 1 Dime 1 0 Quarter 1 1
When a valid coin is inserted, the values of A and B are asserted as shown above, and are reset to zero after the next rising edge of the clock. This prevents the signals A and B from being asserted for more than one clock cycle when a single coin is inserted. Your FSM will take A and B as inputs, and produce outputs V and C. A rising edge on V (vend) will cause the door lock to open, and the lock will remain open until the buyer closes the door. It is not necessary to assert V for more than one clock cycle in order to do this. The output C is normally 1. If C is 0 on the rising edge of the clock, then a nickel will be returned as change. If the buyer deposits more than 35 cents, then your FSM must return the difference in nickels. You may assume that there is an inexhaustible supply of nickels available for change. 1. Draw a state transition diagram for your design. 2. Choose a suitable state assignment. 3. Determine the state transition table. Include the excitations for JK flip-flops. 4. Determine the state and output logic. 5. Draw the circuit schematic.
Stat
e Tr
ansi
tion
Dia
gram
1.
N
icke
l Dep
osits
.
• N
ote
that
stat
es a
re la
bele
d w
ith th
e ou
tput
val
ues V
C, a
nd tr
ansi
tions
are
labe
led
with
the
inpu
t val
ues A
B.
•
Als
o no
te th
at fo
r sta
tes R
eset
, 5c,
…, 3
0c, F
SM re
mai
ns in
that
stat
e w
hen
AB
=00,
but
this
is n
ot sh
own
in th
e di
agra
m.
R
eset
01
5c 01
10c
01
15c
01
01
20c
01
01
25c
01
01 01
01
30c
0101
Ope
n11
01
XX
2.
Mak
ing
Cha
nge.
•
The
buye
r may
dep
osit
as m
uch
as 5
5 ce
nts t
otal
, so
the
FSM
mus
t be
able
to re
turn
up
to 2
0 ce
nts c
hang
e.
• O
nce
the
tota
l dep
osite
d ex
ceed
s 35
cent
s, ch
ange
is re
turn
ed n
o m
atte
r wha
t the
inpu
ts a
re.
R
eset
01
5c 01
10c
01
15c
01
01
20c
01
01
25c
01
01 01
01
30c
0101
Ope
n11
01
40c
00
XX
45c
00
XX
50c
00
55c
00
XX
XX
XX
3.
Dim
e D
epos
its.
R
eset
01
5c 01
10c
01
15c
01
0110
20c
01
01
25c
01
01 01
01
30c
0101
Ope
n11
01
40c
00
XX
45c
00
XX
50c
00
55c
00
XX
XX
10
10
10
1010
10
XX
Res
et01
5c 01
10c
01
15c
01
0110
20c
01
01
25c
01
01 01
01
30c
0101
Ope
n11
01
40c
00
XX
45c
00
XX
50c
00
55c
00
XX
XX
10
10
10
1010
10
11
1111
11
11
1111
XX
4.
Qua
rter D
epos
its
State Transition Table
Present Next State Outputs State AB=00 AB=01 AB=10 AB=11 VC Reset Reset 5c 10c 25c 01
5c 5c 10c 15c 30c 01 10c 10c 15c 20c Open 01 15c 15c 20c 25c 40c 01 20c 20c 25c 30c 45c 01 25c 25c 30c Open 50c 01 30c 30c Open 40c 55c 01
Open Reset Reset Reset Reset 11 40c Open Open Open Open 00 45c 40c 40c 40c 40c 00 50c 45c 45c 45c 45c 00 55c 50c 50c 50c 50c 00
State Assignment
State Q3 Q2 Q1 Q0Reset 0 0 0 0
5c 0 0 0 1 10c 0 0 1 1 15c 0 1 0 1 20c 0 1 0 0 25c 1 0 1 0 30c 1 1 1 1
Open 1 1 1 0 40c 1 0 1 1 45c 1 1 0 1 50c 1 1 0 0 55c 1 0 0 0
State Assigned Table
Present Next State Outputs State AB=00 AB=01 AB=10 AB=11 VC 0000 0000 0001 0011 1010 01 0001 0001 0011 0101 1111 01 0010 XXXX XXXX XXXX XXXX XX 0011 0011 0101 0100 1110 01 0100 0100 1010 1111 1101 01 0101 0101 0100 1010 1011 01 0110 XXXX XXXX XXXX XXXX XX 0111 XXXX XXXX XXXX XXXX XX 1000 1100 1100 1100 1100 00 1001 XXXX XXXX XXXX XXXX XX 1010 1010 1111 1110 1100 01 1011 1110 1110 1110 1110 00 1100 1101 1101 1101 1101 00 1101 1011 1011 1011 1011 00 1110 0000 0000 0000 0000 11 1111 1111 1110 1011 1000 01
State logic for D3
Q3Q2
00
0
1
1
0
1
X
X
X
0
1
0
X
1
1
Q1Q001 11 10
00
01
11
10
00
AB=00
Q3Q2
00
1
1
1
0
1
X
X
X
0
1
0
X
1
1
Q1Q001 11 10
00
01
11
10
00
AB=01
Q3Q2
00
1
1
1
1
1
X
X
X
0
1
0
X
1
1
Q1Q001 11 10
00
01
11
10
00
AB=10
Q3Q2
11
1
1
1
1
1
X
X
X
0
1
1
X
1
1
Q1Q001 11 10
00
01
11
10
00
AB=11
⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡⎟
⎠⎞⎜
⎝⎛ +++++=
+++++=
0Q2BQB2QA3Q0Q1Q2Q3Q0Q2Q3QB3QAB2Q3QA0Q3Q1Q3Q2Q3Q3D
State Logic for D2
0 0 0 X
1 1 X X
1 0 1 0
1 X 1 0
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=00
0 0 1 X
0 1 X X
1 0 1 0
1 X 1 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=01
0 1 1 X
1 0 X X
1 0 0 0
1 X 1 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=10
0 1 1 X
1 0 X X
1 0 0 0
1 X 1 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=11
⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡
⎥⎦⎤
⎢⎣⎡
⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡
⎥⎦⎤
⎢⎣⎡⎟
⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡
++
+++++=
+++
++++=
0QA1Q0Q1Q3Q
3QA0Q1QA3QB0Q2Q1BQ1Q0QA2Q0Q1Q2AQ1Q2QB1Q2QA
0Q2QA0Q2Q3QB0Q1Q3QA0Q2Q3QA0Q1Q3Q2D
State Logic for D1
1 1 1 X
0 1 X X
0 1 0 0
0 X 1 0
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=11
1 0 0 X
1 1 X X
0 1 1 0
0 X 1 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=10
0 0 1 X
0 0 X X
0 1 1 0
0 X 1 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=00
0 1 0 X
1 0 X X
0 1 1 0
0 X 1 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=01
( ) ( )
( )
( ) ⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡
⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡⎟
⎠⎞⎜
⎝⎛
⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡
+++
++++
⊕+⊕+=
+++++
+++++=
1QAB0Q2Q3Q00Q2Q3Q
10Q2Q3Q1QAB0Q2Q3Q1QA1QBA0Q2Q3Q
BA0Q2Q3Q1QAB0Q2Q3QA0Q2Q3Q2Q3QAB0Q1Q2AQ0Q3QBA0Q1Q2QB0Q2Q3QBA
1Q2Q3QB0Q3QB1Q2Q3QA0Q2Q3Q0Q3QA0Q1QBA1D
State Logic for D0
0 1 0 X
1 1 X X
1 1 0 0
0 X 0 0
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=11
1 1 0 X
1 0 X X
1 1 1 0
0 X 0 0
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=10
0 1 1 X
0 1 X X
1 1 1 0
0 X 0 0
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=00
1 1 1 X
0 0 X X
1 1 0 0
0 X 0 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=01
⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡⎟
⎠⎞⎜
⎝⎛
⎟⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡⎥⎦⎤
⎢⎣⎡⎟
⎠⎞
⎜⎝⎛
⎥⎦⎤
⎢⎣⎡⎟
⎠⎞⎜
⎝⎛
⎟⎠⎞⎜
⎝⎛
⎟⎠⎞⎜
⎝⎛⎟⎠⎞⎜
⎝⎛⎟⎠⎞⎜
⎝⎛⎟⎠⎞⎜
⎝⎛
⎟⎠⎞⎜
⎝⎛⎟⎠⎞⎜
⎝⎛⎟⎠⎞⎜
⎝⎛⎟⎠⎞⎜
⎝⎛
+++++•
++++++++++=
+++•
++++++++++•
++++++++++=
0QB1Q2QA1Q2QB
0QBABA2Q3Q3QA1Q0QB0Q1Q2Q3Q
0Q2QBA0Q2Q3QBA1Q2QA1Q2QB0Q1QB2Q3QBA0Q3QBA0Q2Q3Q1Q2Q3Q0D
Output Logic for V
0 0 0 X
0 0 X X
0 0 0 1
0 X 0 0
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=11
0Q1Q2QV =
Output Logic for C
1 1 1 X
1 1 X X
0 0 1 1
0 X 0 1
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
AB=11
0Q1Q1Q2Q3QC ++=
Final Design
Q2
Q3
Q0AQ0
Q2
A
BQ3
AQ1
Q0
Q3
Q1
B
A
Q1
Q0
01
01
01
01234567
Q3
Q2
Q0
A
AQ1
BAB
01
Q1
AB A
10A
B
Q1
Q1
Q
QSET
CLR
D
Q
QSET
CLR
D
B
Q1
Q2
Q2
Q3BA
Q0
AB
A
Q2
Q1BQ0
B
Q0
Q1AQ3
Q1
Q0
Q3
Q2
Q
QSET
CLR
D
Q
QSET
CLR
D
D3
D2
D1
CLK
Q2
Q1
Q3
Q0D0
C
V
Q0
B
A
Q3
Q1
Q0
Q2
Q2
Q3
BQ2
State Transition Table
Present Next State Outputs State AB=00 AB=01 AB=10 AB=11 VC Reset Reset 5c 10c 25c 01
5c 5c 10c 15c 30c 01 10c 10c 15c 20c Open 01 15c 15c 20c 25c 40c 01 20c 20c 25c 30c 45c 01 25c 25c 30c Open 50c 01 30c 30c Open 40c 55c 01
Open Reset Reset Reset Reset 11 40c Open Open Open Open 00 45c 40c 40c 40c 40c 00 50c 45c 45c 45c 45c 00 55c 50c 50c 50c 50c 00
One-Hot State Assignment
State Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Reset 0 0 0 0 0 0 0 0 0 0 0 1
5c 0 0 0 0 0 0 0 0 0 0 1 0 10c 0 0 0 0 0 0 0 0 0 1 0 0 15c 0 0 0 0 0 0 0 0 1 0 0 0 20c 0 0 0 0 0 0 0 1 0 0 0 0 25c 0 0 0 0 0 0 1 0 0 0 0 0 30c 0 0 0 0 0 1 0 0 0 0 0 0
Open 0 0 0 0 1 0 0 0 0 0 0 0 40c 0 0 0 1 0 0 0 0 0 0 0 0 45c 0 0 1 0 0 0 0 0 0 0 0 0 50c 0 1 0 0 0 0 0 0 0 0 0 0 55c 1 0 0 0 0 0 0 0 0 0 0 0
State Assigned Table
Hot Present Next State Outputs Bit State AB=00 AB=01 AB=10 AB=11 VC Q0 000000000001 000000000001 000000000010 000000000100 000000100000 01 Q1 000000000010 000000000010 000000000100 000000001000 000001000000 01 Q2 000000000100 000000000100 000000001000 000000010000 000010000000 01 Q3 000000001000 000000001000 000000010000 000000100000 000100000000 01 Q4 000000010000 000000010000 000000100000 000001000000 001000000000 01 Q5 000000100000 000000100000 000001000000 000010000000 010000000000 01 Q6 000001000000 000001000000 000010000000 000100000000 100000000000 01 Q7 000010000000 000000000001 000000000001 000000000001 000000000001 11 Q8 000100000000 000010000000 000010000000 000010000000 000010000000 00 Q9 001000000000 000100000000 000100000000 000100000000 000100000000 00 Q10 010000000000 001000000000 001000000000 001000000000 001000000000 00 Q11 100000000000 010000000000 010000000000 010000000000 010000000000 00
State and Output Logic for the One-Hot State Assignment The state logic expressions can be found without K-maps. For example, note that from state 000010000000 (Open) the next state is always 000000000001 (Reset), for any input values. The only other way to reach state 000000000001 is from the same state when the inputs are AB = 00.
= +D Q Q A70 0 B
The state logic for the other flip-flops expressions can be found in similar fashion.
= +
= + +
= + +
= + +
= + +
= + +
D Q AB Q AB1 1 0D Q AB Q AB Q AB2 2 1 0D Q AB Q AB Q AB3 3 2 1D Q AB Q AB Q AB4 4 3 2D Q AB Q AB Q AB+Q AB5 5 4 3 0D Q AB Q AB Q AB+Q AB5 46 6 1
Note the pattern in the expressions for D1 through D6. Each could be implemented by a 4:1 MUX with A and B as the select inputs. The state logic for D7 is more complicated because there are seven different present state and input combinations that lead to state 000010000000 as the next state.
= + + +D Q Q AB Q AB Q A7 58 6 2 B Similarly,
= + +
= +
=
D Q Q AB Q A8 9 6 3D Q Q AB49 10
D Q AB10 6
B
7
The output logic can also be determined by inspection. The output V = 1 if and only if the FSM is in state 000010000000 (Open). The output C = 1 if the FSM is in any of the states 000000000001 (Reset) through 000010000000 (Open). Therefore,
+ + +
=
= + + + +
V Q7C Q Q Q Q Q Q Q Q4 50 1 2 3 6
The added cost of the extra flip-flops for this one-hot state assignment is clearly worth it, given the reduction in complexity of the state logic.
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