Modeling Of Combinational Circuits Based On Ternary Multiplexer

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A. Sathish kumar et. al. / (IJCSE) International Journal on Computer Science and Engineering Vol. 02, No. 05, 2010, 1777-1791

i:=i+1; else y<=rol(y); i:=i+1; end if; end loop; end if;

end beh;

Figure 19(a). Block diagram of 2-bit comparator

TABLE III. OPERATING TABLE OF BASIC GATES

A B TAND STNAND PTNAND NTNAND TOR STNOR PTNOR NTNOR

0 0 0 1 1 1 0 1 1 1

0 Z 0 1 1 1 Z Z 1 0

0 1 0 1 1 1 1 0 0 0

Z 0 0 1 1 1 Z Z 1 0

Z Z Z Z 1 0 Z Z 1 0

Z 1 Z Z 1 0 1 0 0 0

1 0 0 1 1 1 1 0 0 0

1 Z Z Z 1 0 1 0 0 0

1 1 1 0 0 0 1 0 0 0

ISSN : 0975-3397 1791

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