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IBM T. J. Watson Research Center
MicroProbe: An Open Source Microbenchmark GeneratorPorted to the RISC-V ISA
Schuyler Eldridge Ramon Bertran Alper Buyuktosunoglu Pradip Bose
7th RISC-V Workshop, 2017
1/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Motivation
Architectural, Design, and Validation Teams have Questions
For my new architecture/design:What is the maximum power consumption?Are there performance bugs?Is my design reliable?. . .
A typical strategy involves writing microbenchmarks
However, microbenchmarks are:Time consuming, tedious and error prone to designNot portable across architectures, microarchitectures, and environment
The expertise for microbenchmark design is limited to a few designers
2/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
MicroProbe: An Automated Microbenchmark Generator
What is it?
A utility for people building microprocessorsA code generation framework that enables advanced microbenchmark generationmethodologies, e.g.:
Microarchitectural-aware test generationPre-silicon and post-silicon tests for power, resilience, and performanceNew research innovations
The internal IBM microbenchmark generator for IBM Power Systems and IBM zSystems [1, 2]
A project led by Ramon Bertran [3, 4]
[1] T. Webel et al. “Robust power management in the IBM z13™,” in IBM Journal of Research and Development. IBM, 2015.
[2] P. I. Chuang et al. “Power supply noise in a 22nm z13™ microprocessor,” in 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017.
[3] R. Bertran et al., “Systematic energy characterization of CMP/SMT processor systems via automated micro-benchmarks,” in 45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2012, Vancouver, BC,Canada, December 1-5, 2012.
[4] R. Bertran et al., “Voltage noise in multi-core processors: Empirical characterization and optimization opportunities,” in 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, UnitedKingdom, December 13-17, 2014.
3/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
MicroProbe: A User’s View
What about... - A loop for each instruction? - A loop with a given instruction distribution? - A loop with certain memory activity? - Inductive noise at a given resonant frequency?
Inputs
MicrobenchmarkGenerationPolicy
ArchitectureDefinition
Files
MicroProbeFramework
Outputs
loop.c
loop.S
loop.bin
Figure: Example use case of a hardware designer wanting to write targeted, microarchitecturally aware benchmarks
4/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Generic Microbenchmark Generation is Difficult...
MicroProbe decouples all aspects
Target Definition using YAMLArchitecture (ISA)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . Necessary work for the RISC-V port
Microarchitecture (ISA implementation)Environment (Operating System, Execution context)
Code Generation using Python
Generation policies using Python
5/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Generic Microbenchmark Generation is Difficult...
MicroProbe decouples all aspects
Target Definition using YAMLArchitecture (ISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Necessary work for the RISC-V portMicroarchitecture (ISA implementation)Environment (Operating System, Execution context)
Code Generation using Python
Generation policies using Python
5/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
MicroProbe Generation Framework
Legend
External
MicroProbeFile
MicroProbeTool
rv8-io: RISC-V ISA Definition
RISC-V ISA Parser
MicroProbe Framework (Python API)
Target Definition
RISC-V ISA Definition
instruction_format.yaml
instruction_field.yaml
register.yaml
register_type.yaml
operand.yaml
instruction.yaml
Microarchitecture Definition
element.yaml element_type.yaml
microarchitecture.yaml
Environment Definition
environment.yaml
Code Generation
Microbenchmark Synthesizer Passes
Design Space Exploration
Search Driver Properties
Generation Policies
fpu-loop.py
l1-l2-load-sequence.py
stress-function.py
max-ipc-search.py
External Tool
External Tool
External Tool
User
microbenchmark.c microbenchmark.S microbenchmark.bin
Figure: MicroProbe generation framework overview: ISA, architecture, and environment definitions describe a targetsystem. User-defined Generation Policies are used to drive microbenchmark generation utilities that may or may notrely on external tools for additional information.
6/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
RISC-V Target ISA DefinitionLegend
External MicroProbe
rv8-ioRISC-V ISA Definition
RISC-VTargetParser
Target Definition
RISC-V ISA Definition
Figure: The composition of a MicroProbe ISA definition: instructions, instruction formats, instruction fields, operands,registers, and register types. This is automatically parsed from the rv8 simulator [1].
[1] M. Clark, “rv8: RISC-V Simulator for x86-64,” Online: https://github.com/rv8-io/rv8, 2017.
7/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
RISC-V Target ISA DefinitionLegend
External MicroProbe
rv8-ioRISC-V ISA Definition
RISC-VTargetParser
Target Definition
RISC-V ISA Definition
instruction.yaml
- Name: "ADD_V0" Mnemonic: "ADD" Opcode: "33" Description: "Add: Add rs2 to rs1 and place the result into rd" Format: "r" Operands: funct5: ['0', 'funct5', '?'] funct2: ['0', 'funct2', '?'] funct3: ['0', 'funct3', '?'] ...
Figure: The composition of a MicroProbe ISA definition: instructions, instruction formats, instruction fields, operands,registers, and register types. This is automatically parsed from the rv8 simulator [1].
[1] M. Clark, “rv8: RISC-V Simulator for x86-64,” Online: https://github.com/rv8-io/rv8, 2017.
7/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
RISC-V Target ISA DefinitionLegend
External MicroProbe
rv8-ioRISC-V ISA Definition
RISC-VTargetParser
Target Definition
RISC-V ISA Definition
instruction.yaml
- Name: "ADD_V0" Mnemonic: "ADD" Opcode: "33" Description: "Add: Add rs2 to rs1 and place the result into rd" Format: "r" Operands: funct5: ['0', 'funct5', '?'] funct2: ['0', 'funct2', '?'] funct3: ['0', 'funct3', '?'] ...
instruction_format.yaml
- Name: "r" Fields: - funct5 - funct2 - rs2 - rs1 - funct3 - rd - opcode Assembly: OPC rd, rs1, rs2 ...
Figure: The composition of a MicroProbe ISA definition: instructions, instruction formats, instruction fields, operands,registers, and register types. This is automatically parsed from the rv8 simulator [1].
[1] M. Clark, “rv8: RISC-V Simulator for x86-64,” Online: https://github.com/rv8-io/rv8, 2017.
7/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
RISC-V Target ISA DefinitionLegend
External MicroProbe
rv8-ioRISC-V ISA Definition
RISC-VTargetParser
Target Definition
RISC-V ISA Definition
instruction.yaml
- Name: "ADD_V0" Mnemonic: "ADD" Opcode: "33" Description: "Add: Add rs2 to rs1 and place the result into rd" Format: "r" Operands: funct5: ['0', 'funct5', '?'] funct2: ['0', 'funct2', '?'] funct3: ['0', 'funct3', '?'] ...
instruction_format.yaml
- Name: "r" Fields: - funct5 - funct2 - rs2 - rs1 - funct3 - rd - opcode Assembly: OPC rd, rs1, rs2 ...
instruction_field.yaml
- Name: "rs1" Size: 5 Description: "rs1" Show: True IO: "I" Operand: "reg"- Name: "funct5" Size: 5 Description: "funct5" Show: False IO: "?" Operand: "imm5" ...
Figure: The composition of a MicroProbe ISA definition: instructions, instruction formats, instruction fields, operands,registers, and register types. This is automatically parsed from the rv8 simulator [1].
[1] M. Clark, “rv8: RISC-V Simulator for x86-64,” Online: https://github.com/rv8-io/rv8, 2017.
7/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
RISC-V Target ISA DefinitionLegend
External MicroProbe
rv8-ioRISC-V ISA Definition
RISC-VTargetParser
Target Definition
RISC-V ISA Definition
instruction.yaml
- Name: "ADD_V0" Mnemonic: "ADD" Opcode: "33" Description: "Add: Add rs2 to rs1 and place the result into rd" Format: "r" Operands: funct5: ['0', 'funct5', '?'] funct2: ['0', 'funct2', '?'] funct3: ['0', 'funct3', '?'] ...
instruction_format.yaml
- Name: "r" Fields: - funct5 - funct2 - rs2 - rs1 - funct3 - rd - opcode Assembly: OPC rd, rs1, rs2 ...
instruction_field.yaml
- Name: "rs1" Size: 5 Description: "rs1" Show: True IO: "I" Operand: "reg"- Name: "funct5" Size: 5 Description: "funct5" Show: False IO: "?" Operand: "imm5" ...
operand.yaml
- Name: reg Description: Integer Registers Registers: x0 : ['x0'] x1 : ['x1'] ...
Figure: The composition of a MicroProbe ISA definition: instructions, instruction formats, instruction fields, operands,registers, and register types. This is automatically parsed from the rv8 simulator [1].
[1] M. Clark, “rv8: RISC-V Simulator for x86-64,” Online: https://github.com/rv8-io/rv8, 2017.
7/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
RISC-V Target ISA DefinitionLegend
External MicroProbe
rv8-ioRISC-V ISA Definition
RISC-VTargetParser
Target Definition
RISC-V ISA Definition
instruction.yaml
- Name: "ADD_V0" Mnemonic: "ADD" Opcode: "33" Description: "Add: Add rs2 to rs1 and place the result into rd" Format: "r" Operands: funct5: ['0', 'funct5', '?'] funct2: ['0', 'funct2', '?'] funct3: ['0', 'funct3', '?'] ...
instruction_format.yaml
- Name: "r" Fields: - funct5 - funct2 - rs2 - rs1 - funct3 - rd - opcode Assembly: OPC rd, rs1, rs2 ...
instruction_field.yaml
- Name: "rs1" Size: 5 Description: "rs1" Show: True IO: "I" Operand: "reg"- Name: "funct5" Size: 5 Description: "funct5" Show: False IO: "?" Operand: "imm5" ...
operand.yaml
- Name: reg Description: Integer Registers Registers: x0 : ['x0'] x1 : ['x1'] ...
register.yaml
- Name: x0 Type: ireg Representation: 'x0' Codification: '0' Description: General Purpose Register 0 Repeat: From: 0 To: 31 ...
Figure: The composition of a MicroProbe ISA definition: instructions, instruction formats, instruction fields, operands,registers, and register types. This is automatically parsed from the rv8 simulator [1].
[1] M. Clark, “rv8: RISC-V Simulator for x86-64,” Online: https://github.com/rv8-io/rv8, 2017.
7/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
RISC-V Target ISA DefinitionLegend
External MicroProbe
rv8-ioRISC-V ISA Definition
RISC-VTargetParser
Target Definition
RISC-V ISA Definition
instruction.yaml
- Name: "ADD_V0" Mnemonic: "ADD" Opcode: "33" Description: "Add: Add rs2 to rs1 and place the result into rd" Format: "r" Operands: funct5: ['0', 'funct5', '?'] funct2: ['0', 'funct2', '?'] funct3: ['0', 'funct3', '?'] ...
instruction_format.yaml
- Name: "r" Fields: - funct5 - funct2 - rs2 - rs1 - funct3 - rd - opcode Assembly: OPC rd, rs1, rs2 ...
instruction_field.yaml
- Name: "rs1" Size: 5 Description: "rs1" Show: True IO: "I" Operand: "reg"- Name: "funct5" Size: 5 Description: "funct5" Show: False IO: "?" Operand: "imm5" ...
operand.yaml
- Name: reg Description: Integer Registers Registers: x0 : ['x0'] x1 : ['x1'] ...
register.yaml
- Name: x0 Type: ireg Representation: 'x0' Codification: '0' Description: General Purpose Register 0 Repeat: From: 0 To: 31 ...
register_type.yaml
- Name: ireg Size: 64 Description: General Purpose Register 64 bits ...
Figure: The composition of a MicroProbe ISA definition: instructions, instruction formats, instruction fields, operands,registers, and register types. This is automatically parsed from the rv8 simulator [1].
[1] M. Clark, “rv8: RISC-V Simulator for x86-64,” Online: https://github.com/rv8-io/rv8, 2017.
7/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
MicroProbe: Flexible and Generic Code Generation
Usage of an Intermediate Representation (IR) of tests
Decouples microbenchmark description from code generation
Any backend can then be targeted, e.g., C, assembly, raw binary
User approach to code generation
User defines a generation policy—a sequence of compiler-like passesAn example policy:
1 Add a building block of 1000 instructions2 Fill the building block with instructions using the floating point unit (FPU)3 All instructions accessing memory should only hit the L14 Set operands to avoid instruction dependencies
8/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example
Approach
1 Start with a QuestionWhat are the latencies and throughputs of RISC-V instructions in Rocket?Or: Can I reverse engineer the Rocket implementation?
2 Write a policyLoop over all instructions while varying dependency distance
3 Emit benchmarksMicroProbe handles this for you . . .
4 Run benchmarks
5 Interpret results
9/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Distance Policy
target = import_definition("riscv_v22-risc_v_generic-riscv64_linux_gcc")
instrs = ['ADD_V0', 'DIV_V0', 'MUL_V0','FADD.S_V0', 'FDIV.S_V0', 'FMUL.S_V0','FADD.D_V0', 'FDIV.D_V0', 'FMUL.D_V0']
loopCount, loopSize, distances = 100, 100, [1, 2, 3, 4, 5]reserved_registers = ["x1", "x2", "x3", "x4", "x8", "x30"]
for instr in filter(lambda x: x.name in instrs, target.isa.instructions.values()):for d in distances:
cwrapper = microprobe.code.get_wrapper("CLoopGen")synth = microprobe.code.Synthesizer(target, cwrapper(loopCount))
passes = [microprobe.passes.structure.SimpleBuildingBlockPass(loopSize),microprobe.passes.instruction.SetRandomInstructionTypePass([instr]),microprobe.passes.initialization.ReserveRegistersPass(reserved_registers),microprobe.passes.register.DefaultRegisterAllocationPass(dd=d) ]
for p in passes:synth.add_pass(p)
bench = synth.synthesize()synth.save('build/' + instr.name + '_' + str(d) + '.c', bench=bench)
Figure: Example benchmark generation via a user-written policy. The user describes a microbenchmark as transformsover an intermediate representation (IR) for describing benchmarks.
10/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Distance Policytarget = import_definition("riscv_v22-risc_v_generic-riscv64_linux_gcc")
instrs = ['ADD_V0', 'DIV_V0', 'MUL_V0','FADD.S_V0', 'FDIV.S_V0', 'FMUL.S_V0','FADD.D_V0', 'FDIV.D_V0', 'FMUL.D_V0']
loopCount, loopSize, distances = 100, 100, [1, 2, 3, 4, 5]reserved_registers = ["x1", "x2", "x3", "x4", "x8", "x30"]
for instr in filter(lambda x: x.name in instrs, target.isa.instructions.values()):for d in distances:
cwrapper = microprobe.code.get_wrapper("CLoopGen")synth = microprobe.code.Synthesizer(target, cwrapper(loopCount))
passes = [microprobe.passes.structure.SimpleBuildingBlockPass(loopSize),microprobe.passes.instruction.SetRandomInstructionTypePass([instr]),microprobe.passes.initialization.ReserveRegistersPass(reserved_registers),microprobe.passes.register.DefaultRegisterAllocationPass(dd=d) ]
for p in passes:synth.add_pass(p)
bench = synth.synthesize()synth.save('build/' + instr.name + '_' + str(d) + '.c', bench=bench)
Figure: Example benchmark generation via a user-written policy. The user describes a microbenchmark as transformsover an intermediate representation (IR) for describing benchmarks.
10/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Distance Policytarget = import_definition("riscv_v22-risc_v_generic-riscv64_linux_gcc")
instrs = ['ADD_V0', 'DIV_V0', 'MUL_V0','FADD.S_V0', 'FDIV.S_V0', 'FMUL.S_V0','FADD.D_V0', 'FDIV.D_V0', 'FMUL.D_V0']
loopCount, loopSize, distances = 100, 100, [1, 2, 3, 4, 5]reserved_registers = ["x1", "x2", "x3", "x4", "x8", "x30"]
for instr in filter(lambda x: x.name in instrs, target.isa.instructions.values()):for d in distances:
cwrapper = microprobe.code.get_wrapper("CLoopGen")synth = microprobe.code.Synthesizer(target, cwrapper(loopCount))
passes = [microprobe.passes.structure.SimpleBuildingBlockPass(loopSize),microprobe.passes.instruction.SetRandomInstructionTypePass([instr]),microprobe.passes.initialization.ReserveRegistersPass(reserved_registers),microprobe.passes.register.DefaultRegisterAllocationPass(dd=d) ]
for p in passes:synth.add_pass(p)
bench = synth.synthesize()synth.save('build/' + instr.name + '_' + str(d) + '.c', bench=bench)
Figure: Example benchmark generation via a user-written policy. The user describes a microbenchmark as transformsover an intermediate representation (IR) for describing benchmarks.
10/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Distance Policytarget = import_definition("riscv_v22-risc_v_generic-riscv64_linux_gcc")
instrs = ['ADD_V0', 'DIV_V0', 'MUL_V0','FADD.S_V0', 'FDIV.S_V0', 'FMUL.S_V0','FADD.D_V0', 'FDIV.D_V0', 'FMUL.D_V0']
loopCount, loopSize, distances = 100, 100, [1, 2, 3, 4, 5]reserved_registers = ["x1", "x2", "x3", "x4", "x8", "x30"]
for instr in filter(lambda x: x.name in instrs, target.isa.instructions.values()):for d in distances:
cwrapper = microprobe.code.get_wrapper("CLoopGen")synth = microprobe.code.Synthesizer(target, cwrapper(loopCount))
passes = [microprobe.passes.structure.SimpleBuildingBlockPass(loopSize),microprobe.passes.instruction.SetRandomInstructionTypePass([instr]),microprobe.passes.initialization.ReserveRegistersPass(reserved_registers),microprobe.passes.register.DefaultRegisterAllocationPass(dd=d) ]
for p in passes:synth.add_pass(p)
bench = synth.synthesize()synth.save('build/' + instr.name + '_' + str(d) + '.c', bench=bench)
Figure: Example benchmark generation via a user-written policy. The user describes a microbenchmark as transformsover an intermediate representation (IR) for describing benchmarks.
10/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Distance Policytarget = import_definition("riscv_v22-risc_v_generic-riscv64_linux_gcc")
instrs = ['ADD_V0', 'DIV_V0', 'MUL_V0','FADD.S_V0', 'FDIV.S_V0', 'FMUL.S_V0','FADD.D_V0', 'FDIV.D_V0', 'FMUL.D_V0']
loopCount, loopSize, distances = 100, 100, [1, 2, 3, 4, 5]reserved_registers = ["x1", "x2", "x3", "x4", "x8", "x30"]
for instr in filter(lambda x: x.name in instrs, target.isa.instructions.values()):for d in distances:
cwrapper = microprobe.code.get_wrapper("CLoopGen")synth = microprobe.code.Synthesizer(target, cwrapper(loopCount))
passes = [microprobe.passes.structure.SimpleBuildingBlockPass(loopSize),microprobe.passes.instruction.SetRandomInstructionTypePass([instr]),microprobe.passes.initialization.ReserveRegistersPass(reserved_registers),microprobe.passes.register.DefaultRegisterAllocationPass(dd=d) ]
for p in passes:synth.add_pass(p)
bench = synth.synthesize()synth.save('build/' + instr.name + '_' + str(d) + '.c', bench=bench)
Figure: Example benchmark generation via a user-written policy. The user describes a microbenchmark as transformsover an intermediate representation (IR) for describing benchmarks.
10/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Distance Policytarget = import_definition("riscv_v22-risc_v_generic-riscv64_linux_gcc")
instrs = ['ADD_V0', 'DIV_V0', 'MUL_V0','FADD.S_V0', 'FDIV.S_V0', 'FMUL.S_V0','FADD.D_V0', 'FDIV.D_V0', 'FMUL.D_V0']
loopCount, loopSize, distances = 100, 100, [1, 2, 3, 4, 5]reserved_registers = ["x1", "x2", "x3", "x4", "x8", "x30"]
for instr in filter(lambda x: x.name in instrs, target.isa.instructions.values()):for d in distances:
cwrapper = microprobe.code.get_wrapper("CLoopGen")synth = microprobe.code.Synthesizer(target, cwrapper(loopCount))
passes = [microprobe.passes.structure.SimpleBuildingBlockPass(loopSize),microprobe.passes.instruction.SetRandomInstructionTypePass([instr]),microprobe.passes.initialization.ReserveRegistersPass(reserved_registers),microprobe.passes.register.DefaultRegisterAllocationPass(dd=d) ]
for p in passes:synth.add_pass(p)
bench = synth.synthesize()synth.save('build/' + instr.name + '_' + str(d) + '.c', bench=bench)
Figure: Example benchmark generation via a user-written policy. The user describes a microbenchmark as transformsover an intermediate representation (IR) for describing benchmarks.
10/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Benchmarks
> ./risc-v_ipc.py
> ls build/*.c | xargs -n5 | column -s' ' -tbuild/ADD_V0_1.c build/ADD_V0_2.c build/ADD_V0_3.c build/ADD_V0_4.c build/ADD_V0_5.cbuild/DIV_V0_1.c build/DIV_V0_2.c build/DIV_V0_3.c build/DIV_V0_4.c build/DIV_V0_5.cbuild/FADD.D_V0_1.c build/FADD.D_V0_2.c build/FADD.D_V0_3.c build/FADD.D_V0_4.c build/FADD.D_V0_5.cbuild/FADD.S_V0_1.c build/FADD.S_V0_2.c build/FADD.S_V0_3.c build/FADD.S_V0_4.c build/FADD.S_V0_5.cbuild/FDIV.D_V0_1.c build/FDIV.D_V0_2.c build/FDIV.D_V0_3.c build/FDIV.D_V0_4.c build/FDIV.D_V0_5.cbuild/FDIV.S_V0_1.c build/FDIV.S_V0_2.c build/FDIV.S_V0_3.c build/FDIV.S_V0_4.c build/FDIV.S_V0_5.cbuild/FMUL.D_V0_1.c build/FMUL.D_V0_2.c build/FMUL.D_V0_3.c build/FMUL.D_V0_4.c build/FMUL.D_V0_5.cbuild/FMUL.S_V0_1.c build/FMUL.S_V0_2.c build/FMUL.S_V0_3.c build/FMUL.S_V0_4.c build/FMUL.S_V0_5.cbuild/MUL_V0_1.c build/MUL_V0_2.c build/MUL_V0_3.c build/MUL_V0_4.c build/MUL_V0_5.c
> ls build/*.c | xargs -n1 -IX riscv64-unknown-elf-gcc X -o X.rv
> ls *.rv | xargs -IX -n1 emulator-freechips.rocketchip.system-DefaultConfig-debug pk X 2>&1 | tee X.log
Figure: Generating, compiling, and running microbenchmarks
11/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Benchmarks
> ./risc-v_ipc.py
> ls build/*.c | xargs -n5 | column -s' ' -tbuild/ADD_V0_1.c build/ADD_V0_2.c build/ADD_V0_3.c build/ADD_V0_4.c build/ADD_V0_5.cbuild/DIV_V0_1.c build/DIV_V0_2.c build/DIV_V0_3.c build/DIV_V0_4.c build/DIV_V0_5.cbuild/FADD.D_V0_1.c build/FADD.D_V0_2.c build/FADD.D_V0_3.c build/FADD.D_V0_4.c build/FADD.D_V0_5.cbuild/FADD.S_V0_1.c build/FADD.S_V0_2.c build/FADD.S_V0_3.c build/FADD.S_V0_4.c build/FADD.S_V0_5.cbuild/FDIV.D_V0_1.c build/FDIV.D_V0_2.c build/FDIV.D_V0_3.c build/FDIV.D_V0_4.c build/FDIV.D_V0_5.cbuild/FDIV.S_V0_1.c build/FDIV.S_V0_2.c build/FDIV.S_V0_3.c build/FDIV.S_V0_4.c build/FDIV.S_V0_5.cbuild/FMUL.D_V0_1.c build/FMUL.D_V0_2.c build/FMUL.D_V0_3.c build/FMUL.D_V0_4.c build/FMUL.D_V0_5.cbuild/FMUL.S_V0_1.c build/FMUL.S_V0_2.c build/FMUL.S_V0_3.c build/FMUL.S_V0_4.c build/FMUL.S_V0_5.cbuild/MUL_V0_1.c build/MUL_V0_2.c build/MUL_V0_3.c build/MUL_V0_4.c build/MUL_V0_5.c
> ls build/*.c | xargs -n1 -IX riscv64-unknown-elf-gcc X -o X.rv
> ls *.rv | xargs -IX -n1 emulator-freechips.rocketchip.system-DefaultConfig-debug pk X 2>&1 | tee X.log
Figure: Generating, compiling, and running microbenchmarks
11/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Benchmarks
> ./risc-v_ipc.py
> ls build/*.c | xargs -n5 | column -s' ' -tbuild/ADD_V0_1.c build/ADD_V0_2.c build/ADD_V0_3.c build/ADD_V0_4.c build/ADD_V0_5.cbuild/DIV_V0_1.c build/DIV_V0_2.c build/DIV_V0_3.c build/DIV_V0_4.c build/DIV_V0_5.cbuild/FADD.D_V0_1.c build/FADD.D_V0_2.c build/FADD.D_V0_3.c build/FADD.D_V0_4.c build/FADD.D_V0_5.cbuild/FADD.S_V0_1.c build/FADD.S_V0_2.c build/FADD.S_V0_3.c build/FADD.S_V0_4.c build/FADD.S_V0_5.cbuild/FDIV.D_V0_1.c build/FDIV.D_V0_2.c build/FDIV.D_V0_3.c build/FDIV.D_V0_4.c build/FDIV.D_V0_5.cbuild/FDIV.S_V0_1.c build/FDIV.S_V0_2.c build/FDIV.S_V0_3.c build/FDIV.S_V0_4.c build/FDIV.S_V0_5.cbuild/FMUL.D_V0_1.c build/FMUL.D_V0_2.c build/FMUL.D_V0_3.c build/FMUL.D_V0_4.c build/FMUL.D_V0_5.cbuild/FMUL.S_V0_1.c build/FMUL.S_V0_2.c build/FMUL.S_V0_3.c build/FMUL.S_V0_4.c build/FMUL.S_V0_5.cbuild/MUL_V0_1.c build/MUL_V0_2.c build/MUL_V0_3.c build/MUL_V0_4.c build/MUL_V0_5.c
> ls build/*.c | xargs -n1 -IX riscv64-unknown-elf-gcc X -o X.rv
> ls *.rv | xargs -IX -n1 emulator-freechips.rocketchip.system-DefaultConfig-debug pk X 2>&1 | tee X.log
Figure: Generating, compiling, and running microbenchmarks
11/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Benchmarks
> ./risc-v_ipc.py
> ls build/*.c | xargs -n5 | column -s' ' -tbuild/ADD_V0_1.c build/ADD_V0_2.c build/ADD_V0_3.c build/ADD_V0_4.c build/ADD_V0_5.cbuild/DIV_V0_1.c build/DIV_V0_2.c build/DIV_V0_3.c build/DIV_V0_4.c build/DIV_V0_5.cbuild/FADD.D_V0_1.c build/FADD.D_V0_2.c build/FADD.D_V0_3.c build/FADD.D_V0_4.c build/FADD.D_V0_5.cbuild/FADD.S_V0_1.c build/FADD.S_V0_2.c build/FADD.S_V0_3.c build/FADD.S_V0_4.c build/FADD.S_V0_5.cbuild/FDIV.D_V0_1.c build/FDIV.D_V0_2.c build/FDIV.D_V0_3.c build/FDIV.D_V0_4.c build/FDIV.D_V0_5.cbuild/FDIV.S_V0_1.c build/FDIV.S_V0_2.c build/FDIV.S_V0_3.c build/FDIV.S_V0_4.c build/FDIV.S_V0_5.cbuild/FMUL.D_V0_1.c build/FMUL.D_V0_2.c build/FMUL.D_V0_3.c build/FMUL.D_V0_4.c build/FMUL.D_V0_5.cbuild/FMUL.S_V0_1.c build/FMUL.S_V0_2.c build/FMUL.S_V0_3.c build/FMUL.S_V0_4.c build/FMUL.S_V0_5.cbuild/MUL_V0_1.c build/MUL_V0_2.c build/MUL_V0_3.c build/MUL_V0_4.c build/MUL_V0_5.c
> ls build/*.c | xargs -n1 -IX riscv64-unknown-elf-gcc X -o X.rv
> ls *.rv | xargs -IX -n1 emulator-freechips.rocketchip.system-DefaultConfig-debug pk X 2>&1 | tee X.log
Figure: Generating, compiling, and running microbenchmarks
11/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Dependency Benchmarks
> ./risc-v_ipc.py
> ls build/*.c | xargs -n5 | column -s' ' -tbuild/ADD_V0_1.c build/ADD_V0_2.c build/ADD_V0_3.c build/ADD_V0_4.c build/ADD_V0_5.cbuild/DIV_V0_1.c build/DIV_V0_2.c build/DIV_V0_3.c build/DIV_V0_4.c build/DIV_V0_5.cbuild/FADD.D_V0_1.c build/FADD.D_V0_2.c build/FADD.D_V0_3.c build/FADD.D_V0_4.c build/FADD.D_V0_5.cbuild/FADD.S_V0_1.c build/FADD.S_V0_2.c build/FADD.S_V0_3.c build/FADD.S_V0_4.c build/FADD.S_V0_5.cbuild/FDIV.D_V0_1.c build/FDIV.D_V0_2.c build/FDIV.D_V0_3.c build/FDIV.D_V0_4.c build/FDIV.D_V0_5.cbuild/FDIV.S_V0_1.c build/FDIV.S_V0_2.c build/FDIV.S_V0_3.c build/FDIV.S_V0_4.c build/FDIV.S_V0_5.cbuild/FMUL.D_V0_1.c build/FMUL.D_V0_2.c build/FMUL.D_V0_3.c build/FMUL.D_V0_4.c build/FMUL.D_V0_5.cbuild/FMUL.S_V0_1.c build/FMUL.S_V0_2.c build/FMUL.S_V0_3.c build/FMUL.S_V0_4.c build/FMUL.S_V0_5.cbuild/MUL_V0_1.c build/MUL_V0_2.c build/MUL_V0_3.c build/MUL_V0_4.c build/MUL_V0_5.c
> ls build/*.c | xargs -n1 -IX riscv64-unknown-elf-gcc X -o X.rv
> ls *.rv | xargs -IX -n1 emulator-freechips.rocketchip.system-DefaultConfig-debug pk X 2>&1 | tee X.log
Figure: Generating, compiling, and running microbenchmarks
11/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Results
1 2 3 4 5Dependency Distance
0.0
0.2
0.4
0.6
0.8
1.0
Inst
ruct
ions
per Cycl
e (IP
C)
ADD MUL DIV FADD.S FMUL.S FDIV.S FADD.D FMUL.D FDIV.D
Figure: Rocket-Chip1 Instructions per Cycle (IPC) as a function of inter-instruction dependency distance
1Using DefaultConfig of 61ef560
12/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Example: Interpreted Results
1 2 3 4 5Dependency Distance
0.0
0.2
0.4
0.6
0.8
1.0
Inst
ruct
ions
per Cycl
e (IP
C)
ADD MUL DIV FADD.S FMUL.S FDIV.S FADD.D FMUL.D FDIV.D
Figure: Rocket Chip per-instruction IPC
Table: Inferred instruction latencies and throughputs
Instruction Latency Throughput
ADD 1 1MUL 4 0.25DIV > 22 < 1
22
FADD.S4 1FMUL.S
FDIV.S
FADD.D6 1
FMUL.D
FDIV.D 4 1
13/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Takeaways
As a user of MicroProbe . . .
Write microbenchmark generators, not benchmarks
14/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Open Source Availability
Caveat
Future location: https://github.com/ibm/microprobe
Pending ongoing legal approval...
15/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Summary
Acknowledgments
This research was developed with funding from the Defense Advanced ResearchProjects Agency (DARPA). The views, opinions and/or findings expressed are those ofthe authors and should not be interpreted as representing the official views or policiesof the Department of Defense or the U.S. Government.
16/16 © 2017 IBM Corporation 7th RISC-V MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
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