MAX 10 - ADCADC •ADC Configuration •2 ADC IP Cores •Altera Modular ADC IP core •Can use...

MAX 10 - ADC

Last updated 10/25/19

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A/D

• Analog to Digital Conversion

• Most of the real world is analog• temperature, pressure, voltage, current, …

• To work with these values in a computer we must convert them into digital representations

• Three steps to this conversion• Sampling

• Quantizing

• Encoding

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A/D

• Sampling

• A to D Conversion takes a finite amount of time

• What if the input changes during this time?

• We must take a snapshot of the input → Sample and Hold

Vin

Sample

Vout

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A/D

• Sampling

• Sampling is a kind of MODULATION

• Modulation systems are subject to Aliasing

• Fin < fs/2

• Fs: Nyquist rate

→ LPF the input

(anti-aliasing filter)

Frequency 0

Frequency 0 fs

Frequency 0fs

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A/D

• Sampling

• Example of analog aliasing

http://arstechnica.com/features/2007/11/audiofile-analog-to-digital-conversion/

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A/D

• Quantizing

• In the A to D process we are converting an “infinite” resolution analog signal into a finite number of digital bits

• Converters use reference voltages to set the range of allowed input voltages - Vref-H , Vref-L

• Each binary step represents

(Vref-H – Vref-L) / 2n for an n bit conversion

• e.g. 0V – 1V input converted to 3 bit

digital value

• each binary step represents 0.125V

• since 000 typically represents 0.0V,

111 represents 0.875V

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A/D

• Quantizing

• Quantization error looks like noise on the signal (Quantization Noise)

• Dynamic Range is a measure of signal to noise ratio. (SNR in dB)

• For an AtoD the Dynamic Range is the measure of signal to Quantizing Noise ratio (SQNR)

• SQNR = 20 log10(2n/(1/2 – (-1/2))

= 20 log102n

• 8bit → 48dB

• 10bit → 60dB

n stepsStep Size

rel toVref-H - Vref-L

SQNR(dB)

1 2 0.5 6

2 4 0.25 12

3 8 0.125 18

4 16 0.0625 24

5 32 0.03125 30

6 64 0.015625 36

7 128 0.0078125 42

8 256 0.00390625 48

9 512 0.001953125 54

10 1024 0.000976563 60

11 2048 0.000488281 66

12 4096 0.000244141 72

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A/D

• A/D Conversion Example

• 10 bit converter with VrefH=3.0V, VrefL=0.0V

• If the input is 2V, what is the output code

VrefH-VrefL = 3V range

10 bit converter step size = range/210 = 2.9297mV/step

2V / 2.9297mV/step = 682 steps from VrefL10 1010 1010

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A/D

• Successive Approximation A to D

• Uses an iterative process to determine the correct digital value for the analog input

• Requires• Input (sample and held)• A register to hold the current estimate of the digital value• D to A converter to convert the digital estimate back to analog• A comparator to determine if the estimate is above or below the

actual input value• Control logic to run the process

• Uses a binary search to find the nearest code value to the input value

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A/D

• Successive Approximation A to D

OutputCode

CONTROL

Successive

Ap

pro

ximatio

n R

egisterD to A

+_

OU

TPU

T LATCH

Vin

Clk

VrefHVrefL

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A/D

• Successive Approximation A to D

OutputCode

CONTROL

Successive

Ap

pro

ximatio

n

Register

D to A

+_

OU

TPU

T LATCH

Vin

Clk

VrefHVrefL

• The control logic resets the SAR before each conversion• The control logic then sets the msb

• The DtoA converts this to ½ the reference voltage• The comparator tests to see if the input is above

or below this value• if above, the 1 in the msb stays• if below, the msb is reset to zero

• The control logic then sets the msb-1 bit• The DtoA converts this to the appropriate voltage

level• The comparator tests to see if the input is above

or below this value• if above, the 1 stays• if below, the msb-1 bit is reset to 0

• The control logic then sets the msb-n bit• The DtoA converts this to voltage• The comparator tests to see if the input

is above or below this value• if above, the 1 stays• if below, the msb-n bit is reset to 0

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A/D

• Successive Approximation A to D• Test to see if input is• > or < new “midpoint”

• if < , clear bit

• if >, set bit

0.96875

0.9375

0.03125

0.0625

0.09375

0.21875

0.1875

0.15625

0.125

0.5625

0.90625

0.875

0.84375

0.8125

0.78125

0.75

0.71875

0.6875

0.65625

0

0.625

0.59375

0.34375

0.3125

0.53125

0.5

0.46875

0.4375

0.40625

0.375

0.28125

0.25Input

Step

s re

lati

ve t

o V

refH

-Vre

fL

Cycle 1

0 0111

Cycle 2 Cycle 3 Cycle 4 Cycle 5

DtoA output

SAR

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ADC

• ADC Configuration• 2 ADC channels

• SAR type conversion

• 12 bit conversion

• 1MHz (max) operation

• 1 dedicated input / channel

• 8 programmable inputs / channel

• 0 – 2.5V conversion range

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ADC

• ADC Configuration

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ADC

• ADC Configuration

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ADC

• ADC Configuration• Special Pre-scaler mode for Channel 8

• Divides input voltage by 2

• Allows input voltages up to 5V with a 2.5V reference

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ADC

• ADC Configuration

• Clocking• Must use PLL for clocking

• PLL1 or PLL3

• Voltage Reference• Internal and external reference options

• Common external reference pin

• Common internal reference

• Can select references separately for each ADC

• Temperature Sensor • ADC1 has an on-die temperature sensor

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ADC

• ADC Configuration

• 2 ADC IP Cores

• Altera Modular ADC IP core• Can use either ADC

• Both cores can be used at the same time

• If both cores used – they will operate asynchronously

• Altera Modular Dual ADC IP core• Instantiates both cores

• ANAIN1 and ANAIN2 inputs are sampled synchronously

• All other pins are asynchronous

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ADC

• ADC Configuration• 4 Configurations for each core

• Standard Sequencer with Avalon-MM Sample Storage• Sequencer manages multiple input pins and sequencing of samples

• Samples are stored in on-chip memory (Sample Store)

• Control – controls the process

• Managed by processor

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ADC

• ADC Configuration• 4 Configurations for each core

• Standard Sequencer with Avalon-MM Sample Storage –Dual Core• Sequencer manages multiple input pins and sequencing of samples

• Merged samples are stored in on-chip memory (Sample Store)

• Control – controls the process independently

• Managed by processor

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ADC

• ADC Configuration• 4 Configurations for each core

• Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection• Adds a splitter

• Compares values to thresholds and provides a violation signal

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ADC

• ADC Configuration• 4 Configurations for each core

• Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection – Dual Core• Adds a splitter

• Compares values to thresholds and provides a violation signal

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ADC

• ADC Configuration• 4 Configurations for each core

• Standard Sequencer with External Sample Storage• Sequencer manages multiple input pins and sequencing of samples

• Control – controls the process

• Managed by processor

• Samples are stored outside the IP core

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ADC

• ADC Configuration• 4 Configurations for each core

• Standard Sequencer with External Sample Storage – Dual Core

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ADC

• ADC Configuration• 4 Configurations for each core

• ADC Control Core Only• Control – controls the process

• Managed by processor

• No Sequencer

• Samples are stored outside the IP core

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ADC

• ADC Configuration• 4 Configurations for each core

• ADC Control Core Only – Dual Core

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ADC

• ADC Configuration• Configuration Blocks

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ADC

• ADC Configuration• Configuration Blocks

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ADC

• ADC Configuration

• 3 approaches to using the ADCs

• Used as part of a NIOS system• Avalon interface built in by Platform Designer

• Used with a hand built interface • Emulate the Avalon interface

• Used with the Quartus ToolKit (Inside System Console) to verify operation• Avalon interface built into the toolkit

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NIOS I/O

• Nios ADC• Create a processor system to use the ADC

Bus Fabric

ADC

ADC Pins

CPU JTAGUART

OnchipMemory Timer

SystemID

ClockReset_bar

M S S S S

CLK

RST

CLK

RST

S

S

PLL ADC CLK

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NIOS I/O

• Nios ADC• Create a processor system to use the ADC• Basic Processor system

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NIOS I/O

• Nios ADC• Create a processor system to use the ADC• ADC components

clk

rstb

dat

a m

aste

r

Notes: requires a locked output from the PLL

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ADC

• Nios ADC• ADC Module

Configuration

Enabled for the Toolkit

Only ADC1 available on DE10-Lite

Max Sample RateRequired Clock

Channel 1Arduino A0 pin

Sequencer Setup

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ADC

• Nios ADC

entity nios_adc_de10 isport(

CLOCK_50 : in std_logic);

end entity;

architecture behavioral of nios_adc_de10 is

component nios_adc isport (

clk_clk : in std_logic := 'X'; -- clkreset_reset_n : in std_logic := 'X' -- reset_n

);end component nios_adc;

begin

u0 : component nios_adcport map (

clk_clk => CLOCK_50, -- clk.clkreset_reset_n => '1' -- reset.reset_n

);end architecture;

---------------------------------------- nios_adc_de10.vhdl---- Created 9/18/18-- by: johnsontimoj-- rev: 0------------------------------------------- Basic Nios system - with adc---------------------------------------

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;

Note: No pin assignments required for ADC pins

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ADC

• Nios ADC• system.h

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ADC

• Nios ADC• system.h

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ADC

• Nios ADC• drivers/inc/altera_modular_adc.h

sequencer andsample/store bases

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ADC

• Nios ADC• User program

ADC operates independently – no pointerto structure or ‘open’ required

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ADC

• Nios ADC• 0.5Hz input

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ADC

• Stand-alone ADC Core

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ADC

• Stand-alone ADC Core

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ADC

• Stand-alone ADC Core

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ADC

• Stand-alone ADC Core

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ADC

• ADC Example – using ADC Toolkit• ADC Module

Configuration

Enabled for the Toolkit

Only ADC1 available on DE10-Lite

Max Sample RateRequired Clock

Channel 1Arduino A0 pin

Sequencer Setup

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• ADC Example – using ADC Toolkit• Platform Planner

ADC

Clk driver required for PLL

10MHz PLL output

ADC Block

Debug interfacefor Toolkit

Toolkit controls theAvalon Interface throughthis module

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• ADC Example – using ADC Toolkit• DE10 top level design

ADC

architecture toplevel of adc_basic_de10 iscomponent adc_basic is

port (clk_clk : in std_logic := 'X'; -- clkreset_reset_n : in std_logic := 'X' -- reset_n

);end component adc_basic;

begin

u0 : component adc_basicport map (

clk_clk => CLOCK_50, -- clk.clkreset_reset_n => '1' -- reset.reset_n

);

-- no activityend architecture;

------------------------------------- adc_basic_de10.vhdl---- by: johnsontimoj---- created: 6/28/2018---- version: 0.0---------------------------------------- ADC example - de10 implementation---- inputs: CLK, ADCin 1 (via IP)---- outputs: none---- Use System Console - ADC Toolkit for validation------------------------------------library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;

entity adc_basic_de10 isport ( CLOCK_50: in std_logic

);end entity;

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ADC

• ADC Example – using ADC Toolkit• Setup

Analog Discovery

DE10-Lite

WaveformOutput Arduino AO pin

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ADC

• ADC Example – using ADC Toolkit

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ADC

• ADC Example – using ADC Toolkit• ADC Toolkit results

Looks like there is a DC offset

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• ADC Control Interfaces• To create a logic controller

ADC

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ADC

• DE10-Lite – ADC WARNINGS

• Only ADC1 is brought out to pins• No access to ADC2 inputs

• The pin #s are shifted• Arduino A0 is mapped to ADC1_in1

…

• Arduino A5 is mapped to ADC1_in6

• No other ADC inputs are pinned out