Marek Perkowski Reversible Logic Synthesis with Garbage Bits Lecture 6

Marek PerkowskiMarek Perkowski

Reversible Logic Reversible Logic Synthesis with Synthesis with Garbage BitsGarbage Bits

Lecture 6Lecture 6

Logic Synthesis for Logic Synthesis for Quantum Pseudo-Quantum Pseudo-

Binary Logic Binary Logic (Permutation Logic)(Permutation Logic)

BackgroundBackgroundReviev of Reversible logicReviev of Reversible logic

This approach is mostly for This approach is mostly for quantum logic realizationquantum logic realization

For optical and CMOS realizations the k*k For optical and CMOS realizations the k*k assumption is not necessarily usedassumption is not necessarily used

Notation for Fredkin GatesNotation for Fredkin Gates

A

0 1 0 1

C B

PQ R

A

0 1

P

B C

Q R

A circuit from two multiplexers

Its schemata

This is a reversible gate, one of many

C AC’+B

BC’+AC

C

A

B

Margolus GateMargolus Gate

A

0 1 0 1

C B

PQ R

A

0 1

C A B

ReversibleReversible

ConservativeConservative

3*3 gate3*3 gate

There are

many similar gates

• The 3 * 3 Toffoli gate is described by these equations: P = A,

Q = B,

R = AB C,

• Toffoli gate is an example of two-through gates, because two of its inputs are given to the output.

Toffoli GateToffoli Gate

P RQ

*

+

A B C

*

+

+

A B

(b)

P Q

*

+

A B C

P RQ

*

+

A B C

P RQ

0 1

KerntopfKerntopf Gate Gate

Feynman

Toffoli

Feynman, Toffoli and

Fredkin gates are their own inverses

• The Kerntopf gate is described by equations: P = 1 A B C AB,

Q = 1 AB B C BC,

R = 1 A B AC.

• When C=1 then P = A + B, Q = A * B, R = B, so AND/OR gate is realized on outputs P and Q with C as the controlling input value.

• When C = 0 then P = A * B, Q = A + B, R = A B.

• 18 different cofactors!

KerntopfKerntopf Gate Gate

Review cofactors if students forgot

• As we see, the 3*3 Kerntopf gate is not a one-through nor a two-through gate.

• Despite theoretical advantages of Kerntopf gate over classical Fredkin and Toffoli gates, so far there are no published results on realization of this gate.

• Is it better for no-ancilla synthesis?

KerntopfKerntopf Gate Gate

Logic Synthesis Logic Synthesis for Reversible for Reversible

LogicLogic

Toffoli

Fredkin

A

B

C

F1D

F2

Feynman

Feynman

How to build garbage-less circuits

GARBAGE BIT 1

GARBAGE BIT 2

We can decrease garbage at the cost of delay and number of gates

We create inverse circuit and add We create inverse circuit and add spies spies for all outputsfor all outputs

2 outputs2 outputs

2 garbages2 garbages

width = 4width = 4

delay = 4delay = 4

Toffoli

Fredkin

ABC

D

Feynman

Feynman

Toffoli

Fredkin

ABC

D

Feynman

Feynman

copy

copy

How to build garbage-less circuits

A,B,C,D are original inputs

inputs reconstructed

This process is informationally reversible

It can be in addition thermodynamically reversible

F1 from spyF2 from spy2 outputs2 outputs

no garbageno garbage

width = 4width = 4

delay = 9delay = 9

ObservationsObservations

• We reduced garbage at the cost of delay and number of gates

• We were not able to reduce the width of the scratchpad register

1. Minimize the garbage

2. Minimize the width of scratchpad register

3. Minimize the total number of gates

4. Minimize the delay

Goals of reversible logic synthesisGoals of reversible logic synthesis

Synthesis Synthesis from from

(p)KFDDs(p)KFDDs

PreprocessingPreprocessing

*+

*+

*+

*+

…...

…...

…...

ci

f1 f2 f3

f4

k1k2 k3

k4 k5 k6

Previous levels

next levels

Other same level

*

+

*

+

*

+

*

+

…...

…...

…...

f1 f2 f3

k1k2 k3

k4 k5 k6

Previous levels

next levels

Other same level

f4

ci

Example of Example of converting a converting a

decision diagram decision diagram to reversible to reversible

circuitcircuit

Starting from Starting from Pseudo-Kronecker Pseudo-Kronecker

Functional Functional Decision DiagramDecision Diagram

f g

pD nD

S S

S

S

S

d

a

b

c

e

1d

d1

0

1

10

0 1

0 1

1 0

10

(a) *+

(b)

*+

d

fG1 G2 g

G3

e

b c

0 0 11a

Starting from Starting from function-driven function-driven

Decision DiagramDecision Diagram

S

S

S

y1

y3

y2

0 1

0

1

1

1

0

0

(b)S

S

S

x4

x3

x1

0 1

0

1

1

10S

x2

S S

S

0

1

01

10

0

0

1

(a)y1 =x2 x3 x1x3 y2 =x3 x1 x1x4 y3 =x1 x4 x3x4 y4 =x4

Converting fDDs to reversible circuitsConverting fDDs to reversible circuits

Standard BDD

Corresponding fDD of Kerntopf

Nonlinear preprocessor

y1 =x2 x3 x1x3 y2 =x3 x1 x1x4 y3 =x1 x4 x3x4 y4 =x4

*

+

*

+*

+

x1

x1

x3

x2

y1

y3

y2

x4

x4

x3

G2

+

x3

1

0 0 11

G1h

G3

Reversible circuit corresponding Reversible circuit corresponding to fDD together with to fDD together with preprocessorpreprocessor

Open Problems:

• Is our set of mapping rules sufficient?– (we have currently about 20 rules, but many

more can be created).

• What is the practically best starting point for large functions? KFDD? PKFDD? fDD?

• How to transform the diagram or the circuit to improve the cost function?

• What to do in case of rule conflict?

• How to create rules to decrease garbage?

Use of Use of ReversibilityReversibility

Observation:Observation:Every synthesis method can be executed

forward and backwards

Sometimes solution backwards can be simpler

A B C D0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

X Y Z V0 0 1 11 0 1 10 0 1 01 0 1 00 0 0 00 1 1 10 0 0 10 1 1 01 1 1 11 0 0 01 1 1 01 0 0 11 1 0 10 1 0 11 1 0 00 1 0 0

Function F Function F -1

X Y Z V0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

A B C D0 1 0 00 1 1 00 0 1 00 0 0 01 1 1 11 1 0 10 1 1 10 1 0 1 1 0 0 11 0 1 10 0 1 10 0 0 11 1 1 0 1 1 0 01 0 1 01 0 0 0

Forward Function Inverse Function

Several methods exist to calculate

inverse from forward function

XToffoli

Fredkin

ABC

Z

YD

VFeynman

Feynman

Toffoli

Fredkin

ABC

Z

Y D

VFeynman

Feynman

X

Circuit for function F

Circuit for function F -1

F*F-1=I

Method of realization of FMethod of realization of F

• 1.1. Find function inverse F-1 of function F.

• 2.2. Synthesize F-1 using any method for reversible gates

• 3.3. Draw the schematics of F-1 from gates.

• 4.4. In the schematics replace every gate by its reverse and change the direction of signals.

• 5.5. The new schematics is the realization of F.

FredkinFredkin AB

C =ZV YZ

Z

Y

D

VFeynman

Feynman

X

X=X=G1G1

Feynman

Feynman

Feynman

G2G2=Z=ZVV0

X

YZ

YZ

Y+Z

ZV

YZZ

0

Y

Y

Y

Fan-out gate

Fan-out gate

We were not able to find the best realization of F-1

shown earlier

Another realization of F-1

Compositions Compositions and and

DecompositionsDecompositions

Composition MethodsComposition Methods

• Composition methods with matching-based cell selection and complexity measures have been presented by:– Dietmeyer– Schneider– Wojcik– Michalski– Jozwiak, Chojnacki and Volf– DeMicheli library matching– Kravets and Sakallah

Uses library of 1*1,2*2 and 3*3 cellsUses library of 1*1,2*2 and 3*3 cells

For every 3*3 function, a ready solution For every 3*3 function, a ready solution cascade is stored - see the results of Kerntopf cascade is stored - see the results of Kerntopf and Storme-DeVosand Storme-DeVos

For every reversible gate, all cofactors can be For every reversible gate, all cofactors can be stored (constants and garbage) and used in stored (constants and garbage) and used in NPN matching.NPN matching.

Gates with more cofactors (like Kerntopf) are Gates with more cofactors (like Kerntopf) are betterbetter

Can be applied to both Can be applied to both classical reversible and classical reversible and

quantum logicquantum logic

Can be applied to both Can be applied to both classical reversible and classical reversible and

quantum logicquantum logic

All intermediate functions

calculated in terms of input

variables

All intermediate functions

calculated in terms of input

variables

Uses equivalence mapping transformations Uses equivalence mapping transformations based on NPN-equivalencebased on NPN-equivalence

Synthesis from inputs to outputs and from Synthesis from inputs to outputs and from outputs to inputs, backtracking and look-ahead outputs to inputs, backtracking and look-ahead strategiesstrategies

How to select the cell, its alignment and constants?

• Select the gate that provides smallest complexity evaluation of the remaining functions and intermediate functions.

• This works for both forward and backward transformations

• I proposed PPRM for matching because it is easy to implement. Other representations and measures can be used for matching - De Micheli, Dietmeyer, Jozwiak.

• Solve exor equations to find inverse functions and input values. Sometimes Kmaps are easier to use.

0

0

1

1

a

+

+

a

c

b

x

yb

c ab

c ab

a

a

Second stageSecond stage of decomposition: Fredkin gate

First stageFirst stage of decomposition: Feynman gate

Decompositional Decompositional synthesis of Toffoli Gate synthesis of Toffoli Gate from Fredkin and from Fredkin and Feynman GatesFeynman Gates

s

t

Third stageThird stage of decomposition: Feynman gate

Using PPRM representation allows for NPN matching and good evaluation of the remaining

function complexity

Direction of synthesis

0

0

1

1

a

+

+

a

c

b

x

yb

c ab

c ab

a

a

Second stageSecond stage of composition: Reversible Expansion for Fredkin gate

Third stageThird stage of composition: Feynman gate

Compositional Compositional synthesis synthesis of Toffoli Gate from of Toffoli Gate from Fredkin and Feynman Fredkin and Feynman GatesGates

s

t

First stageFirst stage of composition: Feynman gate

NPN matching takes care of permutations and inverters

Direction of synthesis

CompositionCompositionFrom inputs to From inputs to

outputsoutputsWhat to do if the initial function is not reversible?What to do if the initial function is not reversible?

A B C

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

X Y Z

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 1

1 1 0

h=AB g=A*B G

0 0 -

0 0 -

1 0 -

1 0 -

1 0 -

1 0 -

0 1 -

0 1 -

Toffoli

Z=A*B

Restrict to C=0Restrict to C=0

3. Toffoli gate assumed.

4. New functions X,Y,Z created.

5. C=0 restriction taken

6. Functions h and g of X,Y,Z can be now realized

CompositionComposition

1. These are inputs

2. These are outputs

ToffoliFeynmanA

B

C

X=A

Y=B

=0

Z=AB

G =X=A

g=Z=AB

h=XY=AB

Created firstCalculated in terms of new variables

X,Y,Z and selected Feynman gate

Compositional synthesis of non-reversible Compositional synthesis of non-reversible function of half-adderfunction of half-adder

garbage

IDEA: Look to outputs, modify

near inputs, reduce the difference

Adder is composed from half-addersAdder is composed from half-adders

2 garbage bits and one constant2 garbage bits and one constant

Compositional synthesis is here top-down, hierachical,

like in classical CMOS

ToffoliFeynmanA

B

C

X=A

Y=B

=0

Z=AB

G =X=A

g=Z=AB

h=XY=AB

Another variant assumes Kerntopf gateAnother variant assumes Kerntopf gate

Heuristics for finding simplest reversible function during composition

CCN CNAB0

AA B (Sum)

A and B (Carry)

ToffoliFeynman

AB

AB 0

AB

00 10 01 10

Mapping of a half-adder

00 01 11 10

This is what we would like to have

But this is not reversible,

A

B

A B

A * B

CCN CNAB0

AA B (Sum)

A and B (Carry)

ToffoliFeynman

AB

AB 0 Mapping of a half-adder

AB

00 10 01 10

00 01 11 10

A

B

A B

A * B

The simplest way to separate them is to add

variable A

Heuristics for finding simplest reversible function during composition

CCN CNAB0

AA B (Sum)

A and B (Carry)

ToffoliFeynman

AB

AB 0

AB

000 010 101 110

Mapping of a half-adder

00 01 11 10

This is what we would like to have But this is not reversible,

because more outputs than inputs

A * B

A

B

A BA

Heuristics for finding simplest reversible function during composition

CCN CNAB0

AA B (Sum)

A and B (Carry)

ToffoliFeynman

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

AB

AB 0

ABC

001 011 100 111

000 010 101 110

Mapping of a half-adder

Positive Davio Gate

Now function is reversible of A,B,C arguments. But we still need to decompose it to known gates

A * B C

A

B

C

A BA

Heuristics for finding simplest reversible function during composition

• Search is defined by:– selecting function to be realized– selecting a gate type– selecting its forward or backwards matching– selecting other signals to match– selecting constant

Garbage functions are becoming less and less undefined in the process of decomposition

They can be used for synthesis

We adopt classical AI search algorithms

(depth-first, breadth-first, A*,best bound, etc)

SearchSearch

• Search cannot be avoided

• Trade-off between quality of solution and search time

• The only real improvement is possible through better selection heuristics and better implementation of cell library.

SearchSearch

b

0 1 0 1

a c

Q

g1 = ab + bc

a

R

P

0 1 0 1

1 c

G2 = b + c

+start

forward backward

H= c+b

forward+

G3

*

c

G4

Library matching

Illustration of cooperation of cooperation of various methodsvarious methods to design the Kerntopf gate from Fredkin, Toffoli, Feynman gates and inverters. One fan-out gate for input a, inverter for c and two fan-out gates for c are not shown.

Adaptations of Adaptations of functional functional

decomposition decomposition methodsmethods

G

H

...

... G

H

...

... G

H

...

...

Ashenhurst-likeAshenhurst-like

parallelserial

New CurtisNew CurtisCurtis-likeCurtis-like

•During graph coloring of an incompatibility graph for nodes with minterms of bound set, two conditions are satisfied:

•there must be 4 colors

•every color must be used exactly 2 times.

G

H

...

...

We sacrifice this wire for

garbageThese two signals should be encoded using 4 symbols

Bound set

Curtis DecompositionCurtis Decomposition

•Probability of finding such coloring is increased by having more don’t cares

•More don’t cares are created by repeating variables in bound and free sets.

•This principle is the base of all decompositions of reversible functions and relations.

Curtis DecompositionCurtis Decomposition

Levelized Levelized StructuresStructures

Two-DimensionalTwo-Dimensional Lattice Diagrams Lattice Diagrams

for reversible logicfor reversible logic

Three Types of General Expansions

f

0 1A

f0 f1

f and A f0 and f1

Forward Shannon

This is a classical Shannon that you

know

Three Types of General Expansions

g,h and A g1A+h0A’

10 1 0

g1

h

A

g1A+h0A’

Reverse Shannon

(b)ho

g

This is a reverse Shannon that you

do not know

Observe that this operator re-introduces the variable A in the middle, the variable that has been reduced in

Shannon.

Three Types of General Expansions

g1A+h0A’

A

g h

10

g0A’+h1A

g, h, and A g0A’+h1A and g1A+h0A’

Reversible Shannon

This is a reversible Shannon that you

do not know

0 1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 0 1 0

- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -

0 1 1 1

100 1

fgarbageg

garbage

garbage

1 010

Z

garbage

fg

X

garbagegarbage gfh i

Y

1

garbagehfg fgh

YZ

X

YZ

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -

- - - -

X

YZX

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 1

1

1

00

0

1

YZX

00 01 11 10

0 1

Shannon lattice uses only half of

each gate

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -0 1 1 1

- - - -- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -- - - -

1 0 1 0- - - -

X

Y

Z

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 0 1 0

0 1 1 1

- - - -- - - -

X

- - - -- - 1 1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -- - - -

- - 1 0- - - -

1 - - -- 1 - -

- 0 - -0 - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

= 1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 0 - -- - - -

- - - -0 1 - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

=1 =0=1 =0

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - 1 -

- - - -

- - - 0- - - -

YZ

This method is fully algorithmic

Variable order selection problem

Expansion type selection problem

Applications of levelized expansion Applications of levelized expansion methodmethod

• This method can be used to create arbitrary circuits, not only lattices

• Any constraint on layout size or shape can be imposed.• The expansion method can be used as the last-resort last-resort

approachapproach when other methods cannot find solution, in order to reduce the number of variables

• It introduces garbage and constants, but this is unavoidable when functions are not balanced

• When realizing multi-output functions start from those that are balanced or closest to balanced.

Conclusions• New concepts:

– (1) Reversible Shannon Expansion for k*k binary Fredkin Gates (k>2) and generalizations - reversible decision diagrams,

– (2) Reversible Fredkin Lattice structures for logic based on binary Fredkin gates,

– (3) Generalized Composition-Decomposition Methods– (4) Adaptations of Ashenhurst/Curtis decompositions.– (5) Levelized expansions for Shannon and Davio-like

gates.– (6) adaptation of BDD-based, decomposition-based and

technology mapping methods from standard binary logic

Research topics

(1) Multiple-valued reversible gates

(2) Multiple-valued quantum logic and synthesis methods

(3) Fuzzy reversible logic and synthesis methods

(4) Ashenhurst/Curtis-like decompositions of multi-valued reversible logic

(5) Levelized expansions for multi-valued Shannon and Davio-like gates.

(6) Decision Diagrams for binary and MV reversible logic

(7) Genetic Algorithm combined with search for quantum logic

(8) Regular structures for MV unate, symmetric, threshold and other functions

(9) Visual Software

End of Lecture 6End of Lecture 6