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March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
1
Nitin Yogi and Dr. Vishwani D. AgrawalAuburn UniversityDepartment of ECEAuburn, AL 36849, USA
N-Model Tests for VLSI Circuits
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
2
Outline Multiple fault models
Importance Minimization problem
Proposed Multiple Fault Model Test Minimization Obtain Fault Dictionary Solve Integer Linear Program (ILP)
Proposed Combined ILP model ILP Model Results
Hybrid LP-ILP method Algorithm Results
Conclusion
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
3
Principle of Testing
Circuit under test
Input patterns
Output responses
Comparator Database
011….101
101….100……….………….…100….001
01….01
…….…
10….11
11….00
Expected correct output
responses
Test ResultsCircuit
Pass/Fail ?
…….…
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
4
Physical Defects in VLSI chips
Polysilicon bridge between two transistor gates.(Reference: EE times, Article: “Good bridge testing needed” by Greg Aldrich and Brady Benware)
Electrical open connection (Reference: Alex A. Volinsky et. al. “FIB failure analysis of memory arrays,” Microelectronic Engineering, Vol. 75, Issue 1, pp 3-11, July 2004.)
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
5
Some Example Fault Models
A
B Stuck-at 0 fault
Stuck-at fault model
Fault-free value
Faulty value
Transition delay fault model
Slow-to-rise faultA
B
Fault-free value
Faulty value
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
6
Multiple Fault Models Importance
Each fault model targets specific defects Sematech study (Nigh et. al. VTS’97) concluded …
To detect most defects, tests for all fault models need to included
Combine test sets covering different fault models Concatenating test sets - number of vectors grows rapidly
Minimization problem Obtain minimized test set for considered fault models
Take advantage of vectors detecting faults in multiple fault models Fault simulator/ATPG handles only one fault model at a time
Need for a new minimization approach
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
7
Conventional Test Vector Minimization (one fault model at a time)
Circuit Type of vecsMentor Fastscan vectors
Fault Cov. (%)
Un-minimized Minimized
c3540
Stuck-at 167 130 96.00
IDDQ(pseudo stuck-at) 53 45 99.09
Transition delay 299 229 96.55
Total 519 404 -
s5378
Stuck-at 150 145 99.30
IDDQ(pseudo stuck-at) 71 70 85.75
Transition delay (LOS) 319 293 98.31
Transition delay (LOC) 256 242 90.05
Total 796 750 -
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
8
Multiple Fault Model Test Minimization
Obtain fault dictionary by fault simulations Determine faults detected by each vector
‘F’ faults : for all considered fault models ‘N’ vectors : generated for all considered fault models
Test minimization by Integer Linear Program (ILP) Set of integer variables Set of constraints Objective function
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
9
Combined ILP Define two [0, 1] integer variables:
{ tj , ij } – for each vector ; j = 1 to N tj = 0 : drop vector j
tj = 1 : select vector j
ij = 0 : no IDDQ measurement for vector j
ij = 1 : measure IDDQ for vector j
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
10
Combined ILP (cont.) Constraints {ck} for kth fault, k = 1 to F
For kth fault detected by vectors u, v and w ck : tu + tv + tw ≥ 1
iu + iv + iw ≥ 1 tu ≥ iu
tv ≥ iv
tw ≥ iw
Only if kth fault
is an IDDQ fault
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
11
Combined ILP (cont.) Objective function
Minimize { ∑ tj + W × ∑ ij } N : total number of vectors tj : variables to select vectors
ij : variables to select IDDQ measurements W : weighting factor, W ≥ 0
How strongly to minimize IDDQ vectors(May depend on the relative cost of current measurement)
j = 1
N
j = 1
N
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
12
Results – Combined ILP
Ckt.
No. of vecs. &
IDDQ meas.
W = 0.1 W = 1 W = 10
Vecs & IDDQ
meas.
CPU$ (s)
Vecs & IDDQ
meas.
CPU$ (s)
Vecs & IDDQ
meas.
CPU$ (s)
c3540Vecs 225
5044*226
5047*247
5047*IDDQ 40 41 37
s5378Vecs 320
2314326
5154*353
5161*IDDQ 78 73 64
* CPU time limit of 5000 s exceeded$ SUN Sparc Ultra 10, four CPU machine with 4.0 GB shared RAM Need for
reducing CPU times
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
13
Hybrid LP – ILP Approximate solution to ILP Algorithm:
1. All variables redefined as real [0,1] real variables (LP model)
2. Loop :1. Solve LP
2. Round variables {tj} , {ij} and add as additional constraints
1. Round to 0 if ( 0.0 < variables ≤ 0.1)
2. Round to 1 if ( 0.9 ≤ variables < 1.0)
3. Exit loop if no variables are rounded
3. Reconvert variables to [0,1] integers and solve ILP
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
14
Results - Hybrid LP - ILP minimization
Ckt.
No. of vecs. & IDDQ meas.
Combined ILP model
ILP solution Hybrid LP – ILP solution
W = 0.1 W = 1 W = 10 W = 0.1 W = 1 W = 10
Vecs / IDDQ
CPU$ (s.)
Vecs / IDDQ
CPU$ (s.)
Vecs / IDDQ
CPU$ (s.)
Vecs / IDDQ
CPU$ (s.)
Vecs / IDDQ
CPU$ (s.)
Vecs / IDDQ
CPU$ (s.)
c3540Vecs 225
5044*226
5047*247
5047*225
167226
189248
516IDDQ 40 41 37 41 39 34
s5378Vecs 320
2314326
5154*353
5161*320
529326
617353
793IDDQ 78 73 64 80 72 63* CPU time limit of 5000 s exceeded
$ SUN Sparc Ultra 10, four CPU machine with 4.0 GB RAM shared among 4 CPUs
Order of magnitude reduction in CPU time
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
15
How Good is Hybrid Optimization?Circuit Weight
(W)Minimized (vectors + W x IDDQ measurements)
Lower Bound ILP Hybrid LP – ILP
c3540 0.1 227.94 229* 229.1
1 257.82 267* 265
10 499.97 617* 588
s5378 0.1 326.76 327.8 328
1 392.28 399* 398
10 910.68 993* 983* CPU time limit of 5000 s exceeded
March 17, 2008
Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana
16
Conclusion Proposed technique
Minimizes test vectors for multiple fault models Minimizes IDDQ measurements.
Cost Trade-off Vector Length and IDDQ measurements
Hybrid LP – ILP procedure reduces time complexity of the solution
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