LECTURE 6: State machines

CWRU EECS 318

EECS 318 CADComputer Aided Design

LECTURE 6: State machines

Instructor: Francis G. Wolff wolff@eecs.cwru.edu

Case Western Reserve University This presentation uses powerpoint animation: please viewshow

CWRU EECS 318

VHDL Component, Entity, and Architecture

Entity

Architecturei

OtherConcurrentComponents

ConcurrentBoolean Equations

Component Instance

Component Declaration

for-generate | if generate

ConcurrentWith-Select-When

When-Else

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VHDL ComponentsComponent Declaration

COMPONENT component_entity_name [ GENERIC ( { identifier: type [:= initial_value ]; } ) ] [ PORT ( { identifier: mode type; } ) ] END;

[ Optional ] { repeat }

Component Instance

identifier : component_entity_name [ GENERIC MAP ( identifier { ,identifier } ) ] [ PORT MAP ( identifier { ,identifier } ) ] ;

mode := IN | OUT | INOUTtype := std_logic | std_logic_vector(n downto 0) | bit

Add ; only if another identifier

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VHDL Concurrent Statements

Boolean Equationsrelation ::= relation LOGIC relation | NOT relation | ( relation )

LOGIC ::= AND | OR | XOR | NAND | NOR | XNORExample: y <= NOT ( NOT (a) AND NOT (b) )

Multiplexor case statement WITH select_signal SELECT

signal <= signal_value1 WHEN select_compare1,• • •

WHEN select_comparen;

Example: 2 to 1 multiplexorWITH s SELECT y <= a WHEN ‘0’, b WHEN OTHERS;

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VHDL Concurrent Statements

Conditionial signal assignment

signal <= signal_value1 WHEN condition1 ELSE• • •

signal_valuen WHEN conditionn; ELSE signal_valuen+1

Example: Priority Encodery <= a WHEN s=‘0’ ELSE b;

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SR Flip-Flop (Latch)

R

S

Q

Q

NANDR S Qn+1

0 0 U0 1 11 0 01 1 Qn

R

S

Q

Q

NORR S Qn+1

0 0 Qn

0 1 11 0 01 1 U

Q <= R NOR NQ;NQ <= S NOR Q;

Q <= R NAND NQ;NQ <= S NAND Q;

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SR Flip-Flop (Latch)

NANDR S Qn+1

0 0 U0 1 11 0 01 1 Qn

R

S

Q

Q

R(t)Q(t)

S(t)Q(t) Q(t + 5ns)

Q(t + 5ns)5ns

5ns

With Delay

Example: R <= ‘1’, ‘0’ after 10ns, ‘1’ after 30ns; S <= ‘1’;

t 0 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns

R 1 1 0 0 0 0 1 1 1Q U U U U 0 0 0 0 0

Q U U U 1 1 1 1 1 1S 1 1 1 1 1 1 1 1 1

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Gated-Clock SR Flip-Flop (Latch Enable)

S

R

Q

QLE

Q <= (S NAND LE) NAND NQ;

Asynchronous: Preset and Clear

Synchronous: Set and Reset

NQ <= (R NAND LE) NAND Q;

CLR

PS

Suppose each gate was 5ns: how long does the clockhave to be enabled to latch the data?

Answer: 15ns

Latches require that during the gated-clock the data must also be stable (i.e. S and R) at the same time

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Rising-Edge Flip-flop

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Rising-Edge Flip-flop logic diagram

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Synchronous Sequential Circuit

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Abstraction: Finite State Machine

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FSM Representations

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Simple Design Example

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State Encoding

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Logic Implementations

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FSM Observations

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Coke Machine Example

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Coke Machine State Diagram

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Coke Machine Diagram II

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Moore Machines

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Mealy Machines