Lecture 5: Pipelining Basicscs6810/pres/6810-05.pdf · 2008. 8. 26. · stage 4 (MEM) and stage 1...

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Lecture 5: Pipelining Basics

• Biggest contributors to performance: clock speed, parallelism

• Today: basic pipelining implementation (Sections A.1-A.3)

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The Assembly Line

A

Start and finish a job before moving to the next

Time

Jobs

Break the job into smaller stagesB C

A B C

A B C

A B C

Unpipelined

Pipelined

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Performance Improvements?

• Does it take longer to finish each individual job?

• Does it take shorter to finish a series of jobs?

• What assumptions were made while answering thesequestions?

• Is a 10-stage pipeline better than a 5-stage pipeline?

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Quantitative Effects

• As a result of pipelining:� Time in ns per instruction goes up� Number of cycles per instruction goes up (note the

increase in clock speed)� Total execution time goes down, resulting in lower

time per instruction� Average cycles per instruction increases slightly� Under ideal conditions, speedup

= ratio of elapsed times between successive instructioncompletions

= number of pipeline stages = increase in clock speed

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A 5-Stage Pipeline

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A 5-Stage Pipeline

Use the PC to access the I-cache and increment PC by 4

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A 5-Stage Pipeline

Read registers, compare registers, compute branch target; for now, assumebranches take 2 cyc (there is enough work that branches can easily take more)

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A 5-Stage Pipeline

ALU computation, effective address computation for load/store

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A 5-Stage Pipeline

Memory access to/from data cache, stores finish in 4 cycles

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A 5-Stage Pipeline

Write result of ALU computation or load into register file

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Conflicts/Problems

• I-cache and D-cache are accessed in the same cycle – ithelps to implement them separately

• Registers are read and written in the same cycle – easy todeal with if register read/write time equals cycle time/2(else, use bypassing)

• Branch target changes only at the end of the second stage-- what do you do in the meantime?

• Data between stages get latched into registers (overheadthat increases latency per instruction)

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Hazards

• Structural hazards: different instructions in different stages(or the same stage) conflicting for the same resource

• Data hazards: an instruction cannot continue because itneeds a value that has not yet been generated by anearlier instruction

• Control hazard: fetch cannot continue because it doesnot know the outcome of an earlier branch – special caseof a data hazard – separate category because they aretreated in different ways

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Structural Hazards

• Example: a unified instruction and data cache �stage 4 (MEM) and stage 1 (IF) can never coincide

• The later instruction and all its successors are delayeduntil a cycle is found when the resource is free � theseare pipeline bubbles

• Structural hazards are easy to eliminate – increase thenumber of resources (for example, implement a separateinstruction and data cache)

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Data Hazards

Example:DADD R1, R2, R3DSUB R4, R1, R5AND R6, R1, R7OR R8, R1, R9XOR R10, R1, R11

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Bypassing

• Some data hazard stalls can be eliminated: bypassing

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Bypassing Example 2

DADD R1, R2, R3LD R4, 0(R1)SD R4, 12(R1)

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Data Hazard Stalls

Not all data hazards can be eliminated!Example:LD R1, 0(R2)DSUB R4, R1, R5AND R6, R1, R7OR R8, R1, R9

Pipeline interlock: hardware that detects this condition and stalls the instruction

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Control Hazards

• Simple techniques to handle control hazard stalls:� for every branch, introduce a stall cycle (note: every

6th instruction is a branch!)� assume the branch is not taken and start fetching the

next instruction – if the branch is taken, need hardwareto cancel the effect of the wrong-path instruction

� fetch the next instruction (branch delay slot) andexecute it anyway – if the instruction turns out to beon the correct path, useful work was done – if theinstruction turns out to be on the wrong path,hopefully program state is not lost

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Branch Delay Slots

• Any ideas on how to deal with data hazards?

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Slowdowns from Stalls

• Perfect pipelining with no hazards � an instructioncompletes every cycle (total cycles ~ num instructions)� speedup = increase in clock speed = num pipeline stages

• With hazards and stalls, some cycles (= stall time) go byduring which no instruction completes, and then the stalledinstruction completes

• Total cycles = number of instructions + stall cycles

• Slowdown because of stalls = 1/ (1 + stall cycles per instr)

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Pipeline Implementation

• Signals for the muxes have to be generated – some of this can happen during ID• Need look-up tables to identify situations that merit bypassing/stalling – the

number of inputs to the muxes goes up

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No action requiredLD R1, 45(R2)

DADD R5, R6, R7DSUB R8, R6, R7OR R9, R1, R7

Dependence with accesses in order

Detect use of R1 during ID of DSUB and set mux control signal that accepts

result from bypass path

LD R1, 45(R2)

DADD R5, R6, R7DSUB R8, R1, R7OR R9, R6, R7

Dependence overcome by forwarding

Detect use of R1 during ID of DADD and stall

LD R1, 45(R2)

DADD R5, R1, R7DSUB R8, R6, R7OR R9, R6, R7

Dependence requiring stall

No hazardsLD R1, 45(R2)

DADD R5, R6, R7DSUB R8, R6, R7OR R9, R6, R7

No dependence

ActionExample codeSituation

Detecting Control Signals

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Summary

• Basic 5-stage pipeline

• Structural and data hazards: bypassing, stalling

• Control hazards: branch delay slots

• Next class: difficulties in pipelining, long latency operations,scoreboarding

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Title

• Bullet