Lecture 11-8253,54 PIT

8253/54PROGRAMMABLE INTERVAL

EE008-3.5-3-MICROPROCESSOR SYSTEMS AND EMBEDDED

SOFTWARE

EE008-3.5-3-Microprocessor Systems and Embedded Software

8253,54-PIT-Programmable Interval Timer sskucti@gmail.com

PIN DIAGRAM OF 8253/54

BLOCK DIAGRAM OF 8253/54

SIMPLE BLOCK DIAGRAM

FEATURES

• There are three counters.• The input frequency can be divided from 1 to 65536.• Input clock frequency is 0-2 MHz for 8253, up to 8

MHz for 8254, and up to 10 MHz for 8254-2.• Shape of the output frequency:• - Square-wave• - One-shot• - Square-wave with various duty cycles.• Gate is used to enable (High) or disable (Low) the

counter.• Bidirectional bus D0-D7 is connected to the system

DESCRIPTION-8254

DATA BUS BUFFER:

• Programming the modes of 8253/54

• Loading the counter registers

• Reading the count values

DESCRIPTION-8254

Read/Write Logic:

• This has five signals:

c. Address lines A0 and A1.

Select Signals

• The control word registers and counters are selected according to the signals on lines A0 and A1.

Programming the 8253/54

• Each counter of the 8253/8254 is individually programmed by writing a control word into the control word register .

Control word format

WRITE OPERATION

1. Write a control word in the control register.

2. Load the low-order byte of a count in the counter register.

3. Load the high-order byte of count in the counter register.

READ Operation

• It is necessary to read the value of the count in some applications

• This is done by three methods

1.Simple Read

2.Counter Latch Command

3.Read-Back Command (Available only for 8254)

MODE 0

• It is used to generate an interrupt to the microprocessor after a certain interval of time.

• The output is initially low after the mode is set. The output remains LOW after the count value is loaded in the counter.

• The process of decrementing the counter continues till the terminal count is reached, i.e., the count become zero and the output goes HIGH. The output remains high until it reloads a new mode of operation or new count.

• The GATE signal is high for normal counting. When GATE goes low counting is terminated and the current count is latched till the GATE goes high again.

MODE 0: Interrupt on terminal count

MODE 1

• The 8253/54 can be used as a mono stable multivibrator.

• The gate input is used as trigger input in this mode. Normally, the output remains high until the count is loaded and a trigger is applied.

• The duration of the quasi stable of the monostable multivibrator is decided by the count loaded in the count register.

MODE 1: PROGRAMMABLE ONE-SHOT

MODE 2

• This is a divide by N counter• The output is normally high after

initialization• If N is loaded as the count value, after N

pulses, the output becomes low for one clock cycle.

• Whenever the count becomes zero another low pulse is generated at the output.

MODE 2: RATE GENERATOR

MODE 3

• This is similar to mode 2.

• When, the count N loaded is EVEN, half of the count will be high and half of the count will be low.

• When, the count N loaded is ODD, the first clock pulse decrements it by 1. Then half of the remaining count will be high and half of the remaining count will be low.

MODE 3: SQUARE WAVE RATE GENERATOR

EXAMPLE 1

• Develop an assembly language program to initialize counter 1 in mode 3 with a count of FECCH. Assume address for control register = 0BH, counter 0 = 08H, counter 1 = 09H and counter 2 = 0AH.

ANSWER 1

• MVI A,76H

• OUT 0BH

• MVI A,CCH

• OUT O9H

• MVI A,FEH

• OUT O9H

EXAMPLE 2

• Determine the counters and control register/port addresses, if the chip select pin of the 8253 PIT is activated by the binary address A7-A2 = 100101.

Answer 2

• Counter 0 = Port Address = 100101 00 = 94H

• Control Register = Port Address = 100101 11 = 97H

EXAMPLE 3

• Determine the configuration of 8253/54, if it’s control register is programmed as follows:

MVI A,36H

OUT ABH

EXAMPLE 4

• Develop an assembly language program to program the counter 1 for a binary count of mode 3 and to divide CLK1 by number B35CH.Assume the port addresses as in Example 2.

ANSWER 4

• MVI A,76H

• OUT 97H

• MVI A,5CH

• OUT 95H

• MVI A,B3H

• OUT 95H

EXAMPLE 5

• Calculate the frequency of OUT2, if CLK2 is divided by C26AH when CLK2 is 1.8 MHz.

ANSWER 5

• The output frequency for OUT2 = 1.8 MHz, is divided by C26AH (49770 D).

• The OUT2 frequency is a square wave of 36Hz.

Lecture 11-8253,54 PIT

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