View
230
Download
0
Category
Preview:
Citation preview
8/18/2019 Layout-Process Anitha Vlsi
1/27
Layout Process
and
Design Rules
8/18/2019 Layout-Process Anitha Vlsi
2/27
Intro
CMOS fabrication can beaccomplished using either of thethree technologies:
• N-well/P-well technologies • win well technolog!
• Silicon On Insulator "SOI#
8/18/2019 Layout-Process Anitha Vlsi
3/27
nMOS $abrication process
hin wafer cut from a single cr!stal ofsilicon
%& to '&(mm ) dia(*+mm thic,ness dopped withimpurities li,e boron
SubstrateP substrate
8/18/2019 Layout-Process Anitha Vlsi
4/27
hic, o.ide "'m#
Step 0: 1a!er of SiO0 is grown o2er the
substrate
Photo 3esist
Step 4: la!er of photo resist to get e2enthic,ness
P substrate
P substrate
8/18/2019 Layout-Process Anitha Vlsi
5/27
56 1ight
Mas,
Step +: e.posing the photo resist la!er witha mas, to the 56 light7 where channel of
transistor is going to place
Ma,es hardene.pect the placewhere di8usion isgoing to be*
P substrate
8/18/2019 Layout-Process Anitha Vlsi
6/27
9indow is created
Step &: tched awa! together with underl!ing silicon*
Step ;: remaining photo resist alsoremo2ed*
8/18/2019 Layout-Process Anitha Vlsi
7/27
Step %: again photo resist and mas,ingallows the Pol!silicon to be patterned
n t!pe di8usion are di8used to form thesource and drain
=i8usion is achie2ed b! heating thewafer to the high temperature andpassing through the gas containing the
desired n t!pe impurit!
P substrate
8/18/2019 Layout-Process Anitha Vlsi
8/27
Step >: thic, o.ide is grown o2er the waferagain and then mas,ed with photo resist to
e.posed selected areas of Pol!silicon gate7source and the drain* " for contact cuts#
Step ?: whole chip is then metal deposited o2erits surface*
8/18/2019 Layout-Process Anitha Vlsi
9/27
1a!out design rules
●Design rules are a set of geometricalspecifications that dictate the design of the
layout masks
● A design rule set provides numerical valuesoFor minimum dimensions
oFor minimum line spacings
●Design rules must be followed to insurefunctional structures on the fabricated chip
●Design rules change with technological
advances (www.mosis.org)
8/18/2019 Layout-Process Anitha Vlsi
10/27
●Why we use design rules
o
!nterface between designer and processengineer
o"uidelines for constructing process masks
o#anufacturing processes have inherent
limitations in accuracy.
oDesign rules specify geometry of masks which
will provide reasonable yields.
oDesign rules are determined by e$perience.
8/18/2019 Layout-Process Anitha Vlsi
11/27
#anufacturing problems
●%hotoresist shrinkage& tearing.
●'ariations in material deposition.
●'ariations in temperature.
●'ariations in o$ide thickness.
●!mpurities.
●'ariations between lots.
●'ariations across a wafer.
8/18/2019 Layout-Process Anitha Vlsi
12/27
ransistor problems
●'ariations in threshold voltage
oo$ide thickness*
oion implantation*
opoly variations.
●+hanges in source,drain diffusion overlap.●'ariations in substrate.
8/18/2019 Layout-Process Anitha Vlsi
13/27
Wiring problems
●Diffusion changes in doping - variations
in resistance& capacitance.
●%oly& metal variations in height& width -variations in resistance& capacitance.
●/horts and opens
8/18/2019 Layout-Process Anitha Vlsi
14/27
0$ide problems
●'ariations in height.
●1ack of planarity - step coverage.
metal 2metal 3
metal 3
8/18/2019 Layout-Process Anitha Vlsi
15/27
'ia problems
●'ia may not be cut all the way through.
●4ndersi5e via has too much resistance.
●'ia may be too large and create short.
8/18/2019 Layout-Process Anitha Vlsi
16/27
Design Rules
#inimum length or width of a feature on a layer is 2
λ
Why
o allow for shape contraction#inimum separation of features on a layer is 3 λ
Why
o ensure ade6uate continuity of the
intervening materials.
8/18/2019 Layout-Process Anitha Vlsi
17/27
Design 7ules
●ypical rules
o#inumum si5e
o#inimum spacingo Alignment , overlap
o+omposition
o8egative features
8/18/2019 Layout-Process Anitha Vlsi
18/27
#0/!/ /+#0/ design rules
●Designed to scale across a wide range of
technologies.
●Designed to support multiple vendors.
●Designed for educational use.
●9rgo& fairly conservative.
●http://www*mosis*com/design/rules/
http://www.mosis.com/design/rules/http://www.mosis.com/design/rules/
8/18/2019 Layout-Process Anitha Vlsi
19/27
1ambda design rules
●λ is the si5e of a minimum feature.
●/pecifying λ particulari5es the scalable
rules.
●%arasitics are generally not specified in
units
8/18/2019 Layout-Process Anitha Vlsi
20/27
ypes of Design 7ules●/calable Design 7ules (e.g. /+#0/)
o:ased on scalable ;coarse grid< - λ(lambda)
o!dea reduce λ value for each new process& but keep rule
the same
=ey advantage portable layout
=ey disadvantage not everything scales the same
o8ot used in ;real life<
8/18/2019 Layout-Process Anitha Vlsi
21/27
● Absolute Design 7ules
o:ased on absolute distances (e.g. >.?@m)
ouned to a specific process (details usually
proprietary)
o+omple$& especially for deep submicron
o1ayouts not portable
8/18/2019 Layout-Process Anitha Vlsi
22/27
9ires
metal 4;
metal 04
metal '4
pdi8/ndi8 4
pol!0
All wire widths are
multiples of
8/18/2019 Layout-Process Anitha Vlsi
23/27
ransistors
0
4
'
40
4
8/18/2019 Layout-Process Anitha Vlsi
24/27
'ias
●ypes of via metal2,diff& metal2,poly&
metal2,metal3.
B
2
B
3
8/18/2019 Layout-Process Anitha Vlsi
25/27
#etal C via
●ype metalC,metal3.
●7ules
ocut C $ C
ooverlap by metal3 2
ominimum spacing Cominimum spacing to via2 3
8/18/2019 Layout-Process Anitha Vlsi
26/27
8/18/2019 Layout-Process Anitha Vlsi
27/27
Recommended