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Title
Number RevisionSize
B
Date: 1/30/2009 Sheet of
INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE
page1
CLKOUTPCLKOUTN
OVDD
DGND
10K R40
D0N
D0P
22
D1N
23
D1P
24
D2N 25D2P 26D3N 27D3P 28OVSS 29
RLVDS 30
CLKOUTN 31CLKOUTP 32
D4N 33D4P 34D5N 35D5P 36OVDD
37
D6N
38D6P
39ORN
U1KAD5514-48
D5N
D6N
D7N
D4P
D5P
D6P
D7P
D8N
D9N
D10
N
D8P
D9P
D10
P
00pF39
0.1u
FC13
0.1u
FC23
pin2
0
pin3
7
100p
FC32
100p
FC33
100p
FC31
100p
FC34
SDIO
CSB
SCLK
SDO
OVDD
OVDD
ormalp
p
rmal
KDC5512P/5512HP/5514P-Q48
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
1
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Schematics
FIGURE 1. ADC, CLOCK AND ANALOG INPUTS, MODE PINS AND POWER SUPPLY BYPASS
coplanar wave guide.
T3
TC4-1W
J4
SMA
200R22
1000pF
C28 C26
1000pF
"CLOCK IN"
J5
SMA
49.9R47
220pFC47
C420.1uF
"CLOCK IN"
49.9R46
1000pFC43
49.9R45
1000pFC45
clk_inp
clk_inn
clk_inp
clk_inn
49.9R49
49.9R48
49.9R50
anlg_3.3V
49.9R43
10000uFC46
1000pF
C25
0.1uFC44
1000pF
C24
anlg_3.3V
C40DNP
C41DNP100
R42
49.9R44
Q1 1
Q1 2
Q2 3
Q2 4
Q3 5
Q3 6
Vcc
7EN
8
IN9 VREFAC10 VT11 IN12
GND
13
Vcc
14
Q0 15
Q0 16
EP0
NB6L14MMNG
U5DNP
VinIm
VinIp
C18DNP
J3SMA
C37
10000pF
Vcm
C35
DNP
C36DNP
0R37
R41DNP
50 Ohms Coplanar Waveguide
50 Ohms differential routing
Tx_VinIm
J2SMA
C20
0.01uF
Vcm
0.1uFC21
0.1uFC16
50 Ohms Coplanar Waveguide
50 Ohms differential routing
1
3
6
4
T1ADTL1-12+0.1uF
C15
Tx_VinIp
0 R39
28R17
28R19
R16DNP
R18DNP
VinIm
VinIpflux_VinIp
flux_VinIm
1
3
6
2
4T4
ADT1-1WT
1
3
6
2
4T5
ADT1-1WT
1
3
6
4
T2ADTL1-12+
R38DNP
0
R15
0
R14
270uH
L7
270uHL9
0.1uF
C14
1uH
L5
1uH
L8
L6Bead
L10Bead
Vcm
Vcm
AVDD
clk_
inp
clk_
inn
DGND
GND
GND
GND
GND DGND
RES
ETN
VinImVinIp
SCLSDA
SDIO
CSB
SCLK
SDO
AVDD
AVDD
AVDD
AVDD
OVDD
Vcm
AVDD1
DNC2
DNC3
DNC4
AVSS5
VINN6
VINP7
AVSS8
AVDD9
VCM10
DNC11
AVSS12
AVDD
13
CLK
P14
CLK
N15
NAPS
LP16
AVDD
17
RES
ETN
18
OVSS
19
OVDD
20 2140
ORP
41
OVSS
42SD
O43
CSB
44SC
LK45
SDIO
46
AVDD
47AVSS
48EP
49
D4N
D11
ND11
P
0.1uFC19
pin4
7
0.1uFC12
0.1uFC17
pin1
pin9
1C
0.1uFC38
pin4
7
0.1uFC22
pin1
6
pin1
0
nap_
sleep_
norm
al
AVDD
AVDD
AVDD
AVDD
Vcm
Place beads under DUT.
beadL16
beadL17
beadL18
beadL15
R20DNP
R211K
LO = NHI= Na
Ft= Slee
nap_sleep_no
anlg_1.8V
nap_
sleep_
norm
al
Title
Number RevisionSize
B
Date: 1/30/2009 Sheet ofFile: \\..\KDC5512-Q48 IO.SchDoc Drawn By:
INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEM
dig_1.8V
SD2SC2
SPARE EEPROM
SC0SD0
ID EEPROM
10K
R28
0.1uFC2
0.1uFC3
4.7K
R23
4.7K
R25
dig_1.8V
WP_2V0R27
0R26
A01
A12
A23
Vss4 SDA 5SCL 6WP 7Vcc 8
U2
24AA64-I/SN
A01
A12
A23
Vss4 SDA 5SCL 6WP 7Vcc 8
U3
24AA32A-I/SN
dig_1.8V
dig_1.8V
WP_2V
L13 Bead
L14 Bead
L4 Bead
100pF
C11
100pF
C9
L3 Bead
SC0
SD0
SCL
SDA
100pF
C10
100pF
C8
KDC5512P/5512HP/5514P-Q48
page2 A
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
2
FIGURE 2. INPUT/OUTPUT MEZZANINE CONNECTOR
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Schematics (Continued)
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121 122123 124125 126127 128129 130131 132133 134135 136137 138139 140141 142143 144145 146147 148149 150151 152153 154155 156157 158159 160161 162163 164165 166167 168169 170171 172173 174175 176177 178179 180
J6
5509-11875
TDITDO TMS
TCK
VCC
I/O(GCK) 1I/O(1) 2I/O(1) 3GND 4I/O(1) 5I/O(1) 6VCCIO1 7IO(1) 8TDI 9TMS 10TCK 11
IO(1)
12IO
(1)
13IO
(1)
14VCC
15IO
(1)
16GND
17I(2)
18IO
(2)
19IO
(2)
20IO
(2)
21IO
(2)
22
IO(2)23
TDO24
GND25
VCCIO226
IO(2)27
IO(2)28
IO(2)29
IO_GLB_S/R30
IO_GOE31
IO_GOE32
IO_GOE33
IO_G
OE
34
VAUX
35
IO(2)
36
IO(2)
37
IO(2)
38
IO(1)
39
IO(1)
40
IO(1)
41
IO(1)
42
IO(G
CK)
43
IO(G
CK)
44
U4XC2C64A-6VQG44C
TDITDO
TMSTCK
1 23 45 67 89 1011 1213 14
J1
2MM HDR 14P SMT
JTAG connector
Dig_5V
Anlg_5V
DGNDGND GND
VCC
SD0SC0SD2SC2
anlg_1.8V
anlg_3.3V
C_vdd3_anlg
VCC
dig_1.8V
PORn_
ExtResetn_
fpga
PC0 daughter card detectedPC1
PC6PC7
PC4PC5
PC2PC3
PC1
Programing PLCD
0.1u
FC4
0.1u
FC29
0.1u
FC30
R3
1K
dig_
1.8V
R6 1K
33uF
C1
0.1u
FC5
VCC
dig_1.8V
4.7KR33
R24
1K
DGND
R31
4.7K
dig_1.8V
PORn_ExtResetn_fpga
CPLD SPARE1SPI_master_drive
R13 1K
R34
1K
R11 1K
4.7K
R2
dig_1.8V
PC2
SPI_CONF
D1PD1N
D2ND2P
D3ND3P
D0PD0N
D4N
D5N
D6N
D7N
D8N
D9N
D10N
D4P
D5P
D6P
D7P
D8P
D9P
D10P
CLKOUTPCLKOUTN
D11N
D12N
D13N
ORN
D11P
D12P
D13P
ORP
R7 1K
R4
1K
R5 1K
CSB
_3V
SCLK
_3V
SPI_master_drive
MISO_3
VMOSI_3
V
SDIOCSB
SCLKSDO
R1 1K
R10 1K
CSB_3VSCLK_3V
MISO_3VMOSI_3V
key face toward center
R8
1K
R35
1K
AVDD
AVDD
OVDDOVDD
R9 1K
R12 1K
PC7
PC6
PC5
PC4
PC3
33uFC27
33uFC6
33uFC7
RES
ETN
R32
1K
dig_1.8V
CPLD SPARE1
R30
1KR29
1K
WP
WP
WP_
2V
R36
1K
dig_
1.8V
dig_
1.8V
VCC
dig_
1.8V
VCC
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers
FIGURE 3. PRIMARY SIDE
3
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
FIGURE 4. GND PLANE 1
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued)
4
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
FIGURE 5. PWR PLANE
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued)
5
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
FIGURE 6. INTERNAL SIGNAL
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued)
6
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued)
FIGURE 7. GND PLANE 2
7
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
FIGURE 8. SECONDARY SIDE
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued)
8
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
FIGURE 9. SECONDARY SIDE SILKSCREEN
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued)
9
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned toverify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
FIGURE 10. LAYER - PRIMARY SIDE SILKSCREEN
KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued)
10
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