Kabuki 2800

Kabuki 2800

Critical Design Review

19 October 2006

Agenda1. System Block Diagram2. Software Processes3. System Specifications and Design4. Test Results and Demo5. Detailed Schedule6. Division of Labor

DSK Starter Kit48KHz A/D48KHz D/A

DSP processing core

Router BoardRouts signals between DSP host and all peripherals

FPGA and PROMUSBRS-232

Performance BoardA/D

Reads input fromo1 foot fader pedalo5 actuators

Communicates with Router Card via RS-232

DSP Co-ProcessoroFFT / IFFT

oCommunicates with DSK via HPI or Router Card

USB displayoTablet or Laptop

oCommunicates with Router Card

Foot Pedal Actuator 1Actuator 2Actuator 3Actuator 4Actuator 5

Audio InAnalog

Audio OutAnalog

Kabuki 2800

Block Diagram

Router: Protocol

• “Kabuki Router Advanced Addressing Protocol”

• Common command and data protocol for all devices

• 24-bit KRAAP packets– 3 bit dest. Module– 5 bit command code– 16 bits of data

R uter: Logic

Router: Logic example

• USB asking UART command handler for input board state information

Software: DSP

• Effects processing magic• Runs on TI DSK• Written entirely in C• Currently ~3k lines of code• Subversion version control

Software: DSP

• Gets preset info from router• Gets inputs from input board or software console

• Sends data to software console for spectral analysis

• Sends data to possible DSP coprocessor

Software: DSP

• Toplevel architecture

Software: DSP

• Possible effect: Single

Software: DSP

• Possible effect: Mixer

Software: DSP

• Possible effect: Complex

Software: Console

• Connects to router via USB• Written entirely in Python• Uses Gtk+ Linux GUI toolkit• ‘Subversion’ version control• Nanobunnies

Software: Console

Router

Function: • Handles I/O from one module to the next

• Brain: – FPGA with FLASH prom/memory

• Ports:– EMIF, RS-232, USB, JTAG

Router Board

Buko the monkey

RS-232

MAX3237

USB

DLP-245

FPGACyclone

II

EMIF

LEDs

74xx TXRX3.3V

1.2V

JTAG

FLASH

PROM

CLK

Buttons

PERIPH.

HPI

Transceiver Logic (USB)

Max RS 3232

• Assembled

• Prototyped

• Capacitors

• Lag time

• Functionality

Prototype Board

DB9 Connector

RS3232

Performance Module Specifications

• Read fader pedal from A/D @12 bits

• Read foot actuator inputs

• Boot from flash prom

• Communicate with Router Board via RS-232 Transceiver at 1MHz

• Debugging LEDs and Switches

Performance Block Diagram

Spartan 3E

A/D Converter

Foot Pedal

Actuators

RS-232 Transceiver

Flash PROMSwitches / LEDs

Performance Module

A/D

Spartan3E FPGA

Actuator Inputs Fader Pedal

JTAG

Switches LEDs

VREG VccAux

VREG VccInt

VREG Vcc

Xilinx PROM

RS232 Transceiver

Reset

Performance Module Design

• Xilinx Spartan 3E FPGA to handle communication with the A/D and Router Card.

• Xilinx PROM to program Spartan 3E• Maxim 3237 RS-232 Megabaud

Transceiver Clock Source: Crystal Oscillator (25-

100MHz)

Performance Module Input

• 5 Foot Actuators• (Connected directly into Spartan)

• 1 Fader Foot Pedal• 3.3 volt signal attenuated through the pedal

• AD7859 (ADC with 12-bit resolution)• High speed• PLCC 44 package: replaceable

• 8 LEDs, 8 Switches, 1 Reset Button

Performance Module Power• Vcc = 3.3 V LDO Regulator LT1086,

stepped down from 5 V

• JTAG, VccAux = 2.5 V LDO Regulator LT1763, stepped down from 3.3 V Regulator

• VccInt = 1.2 V LDO Regulator LT3021, stepped down from 3.3 V Regulator

DSP Co-processor Design

• 200pin HLQFP• Not BGA!!!

• Connection• through Host Peripheral Interface on DSK

• 192K internal SRAM• Maybe enough!

• Clock Source:• same as DSK, 50MHz Crystal Oscillator.

HPI

TMS3206713B-200

DSP C -processor Specifications

• Communication via 225MHz

• Direct Connection to DSK Host

• Transfer 256 samples and FFT / IFFT in <1us

Development Structure

Kabuki 2800

Primary

Secondary

Dan’s Tasks

Primary

• Software Effects• Software Devices

• Software simulation

Secondary

Layout design and fabrication.

Firmware

Kabuki 2800

Justin’s Tasks

Primary

• Router Board Layout

Design and Fab.

• Firmware

• USB design and Protocols

Secondary

Does No have any.

Kabuki 2800

Tim’s Tasks

Primary

• Performance board firmware

• layout and design

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Secondary

USB Design and Protocols

Device Casing

Yazan Task’s

Primary

• Device Casing and Fabrication

• DSK and interface Card

Kabuki 2800

Secondary Module hardware design Module Firmware design Audio effect algorithm

simulation Audio effect algorithm Final packaging and

Software

•Phase 1 – Milestone 1, Nov. 2•Phase 2 – Milestone 2, Nov.

30•Phase 3 – Expo, Dec. 14

ScheduleSchedule

PhasesPhases• Phase 1 –

Development & Prototyping

• Phase 2 – Integration

• Phase 3 – Testing and Production

• Board Fabricated (Done)• FPGA configured (Done)• FPGA boots from PROM (Done)• FLASH reads/writes properly• DSK I/O Firmware Complete• USB tested• RS-232 interface tested

Router BoardRouter BoardPhase 1

• FPGA configured and tested

Router BoardRouter BoardPhase 2

• All interfaces fully functional (RS-232, USB)• Flash storage able to load / store presets• I/O functions with DSK and DSP co-

processor• USB firmware interfaces with FPGA and

with host computer• RS-232 interface fully functioning• Firmware completed and under testing• Communication established with DSP

coprocessor.

Router BoardRouter BoardPhase 3

• PCB Fabricated (In Progress)• FPGA configured and tested• FPGA boots from EEPROM• A/D converter tested• Firmware in testing

Performance BoardPerformance BoardPhase 1

• FPGA interfaces with I/O board • Foot – pedals generate interrupts• A/D converter samples fader pedal

Performance BoardPerformance BoardPhase 2

• FPGA interfaces with Interface Card • All user inputs are fully functional

Performance BoardPerformance BoardPhase 3

•Board Layout Complete

DSP Coprocessor DSP Coprocessor Phase 1

•Board fabricated, populated and ready for testing

•JTAG ready

DSP Coprocessor DSP Coprocessor Phase 2

• DSP Processor is able to implement FFT and Wavelet Transforms

• DSP is able to communicate with I/O board and and co-process transforms

DSP Coprocessor DSP Coprocessor Phase 3

Effect Algorithms Effect Algorithms Phase 1

•Some Time Domain Effects Simulated–Phasing–Filters–Etc.

•Most time domain effects simulated

•Several more time domain effects implemented

•FFTs simulated in Matlab

Effect Algorithms Effect Algorithms Phase 2

• Time Domain effects implemented

• FFT and Wavelet Domain effects simulated and implemented

Effect Algorithms Effect Algorithms Phase 3

Kabuki 2800 Budget

Module Item Cost Qty Shipping Total

Main box I/O board Altera Cyclone or Xilinx Spartan III FPGA $60 2 $10 $130

Main box I/O board 4-layer PCB fabrication $60 3 $10 $190

Main box I/O board USB 2.0 transceiver DSK mezzanine board $100 1 $10 $110

Main box coprocessor board TI DSP $40 2 $10 $90

Main box coprocessor board 4-layer PCB fabrication $60 3 $10 $190

Performance Card 4-layer PCB fabrication $66 2 $10 $142

Performance Card Xilinx FPGA and PROM $30 2 $10 $70

Human input box controls Foot actuators $30 5 $150

Human input box controls Foot pedals $100 1 $100

Box Casing Casing materials + fabrication $160 1 $160

Testing & prototyping Misc audio connectors and converters (1/8", 1/4", XLR) $40 1 $40

MiscMisc electrical components (surface-mount components, LEDs, A/D

converter) $200 1 $200

Sum Total $1,702

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