IP Router Architectures. Outline Basic IP Router Functionalities IP Router Architectures

IP Router Architectures

許凱銘

Outline Basic IP Router Functionalities IP Router Architectures

Generic architecture of a router

Basic architecture Routing components

Basic IP Router Functionalities

Route Processing Routing table construction and maintenance using routing

protocols (such as RIP or OSPF)

Packet Forwardinga) IP Packet Validationb) Destination IP Address Parsing and Table Lookupc) Packet Lifetime Controld) Checksum Calculation

Special Services

Route Table Lookup Major performance bottleneck Longest prefix matching problem(CIDR) Cache IP destination-to-next-hop

association in a separate database the front-end database:hash table (problem:may hash to the same value)

Need efficient lookup method software , hardware

IP Router Architectures Bus-based Router Architectures with

Single Processor Bus-based Router Architectures with

Multiple Processors Architectures with Multiple Parallel

Forwarding Engines Switch-based Router Architectures with

Multiple Processors Switch-based Router Architectures with

Fully Distributed Processors

Bus-based Router Architectures with Single Processor

Traditional bus-based router architecture

Problem Share bus Bottleneck:data cross the bus twice Everything are implemented on the

central processor No Cache in Line Card

Bus-based Router Architectures with Multiple Processors

Architectures with Route Caching Architectures with Multiple Parallel

Forwarding Engines

Architectures with Route Caching

Reducing bus copies using a route cache

Problem:Architectures with Route Caching

Shared bus is the bottleneck Traffic dependent throughput Enhance each of network interface

cards with larger memories and complete forwarding tables can improve performance

Architecture with Multiple Parallel Forwarding Engines

head data

headtagRound-robin

Round-robin

Problem:Architecture with Multiple Parallel Forwarding Engines

Forward engine can work on different header in parallel

Decrease the packet payload transfer over the bus

Switch-based Router Architectures with Multiple Processors

Three stages of forwarding process

1. The following are done in parallel

• Confirm the header is IPv4 datagram• Confirm packet and header lengths are reasonable • Confirm IPv4 header has no option• Computes the hash offset into the route cache and

loads the route• Start loading in the next header

(cont)2. Forwarding engine start if cache hit -> ok else ->

• lookup the extended forward table• update the route cache• checks TTL compute updated TTL and IP

checksum3.

• Put the updated TTL and checksum in IP header• Updated IP header is written out along with link-

layer information from forwarding table

Limitation of IP Packet Forwarding based on Route Caching

how big the cache is how the cache is maintained (the three most

popular cache maintenance strategies are random replacement, (FIFO), (LRU)

what the performance of the slow path is, since at least some percentage of the traffic will take the slow path in any application

Switch-based Router Architectures with Fully Distributed Processors

Three bottleneck in a router:processing power,memory bandwidth,internal bus bandwidth , these can be avoided by using a distributed switch based architecture

Critical Data Path(Fast Path)Non-Critical Data Path(Slow Path)

(cont)