Investigating Error Detection using CRC EE800 Project Presentation

Investigating Error Detection using CRC EE800 Project Presentation

VISHESH11089943

Introduction

CRC generation is mostly implemented using Linear feedback shift Registers using Flip-Flops and XOR gates.

But not many understand how to implement a customized parallel CRC circuit described by an arbitrary CRC generator polynomial.

In this paper importance of parallel architecture is discussed and how it can be incorporated in different styles so as to compare the number of logic cells used for each Architecture.

Serial CRC Implementation

USB CRC5 implementation as LFSR using generator polynomial G(x)=x5+x2+1

The problem is that in many cases shift register implementation is suboptimal. It only allows the calculation of one bit every clock. If a design has 16-bit wide data path,

meaning that every clock CRC module has to calculate CRC on 16-bit of data, this scheme will not work.

M-Bit CRC next state

ParallelCRC

GeneratorN-Bit Data input

M-Bit CRC Output

Parallel CRC Generator

EXAMPLE OF USB CRC5 with N=4, M=5 @ [1],[2],[5]

Every clock N bits are processed.

Mout[0] = Min[1] ^ Min [4] ^ Nin[0] ^ Nin [3]

Mout [1] = Min [2] ^ Nin [1]

Mout [2] = Min [1] ^ Min [3] ^ Min [4] ^ Nin [0] ^ Nin [2] ^ Nin [3]

Mout [3] = Min [2] ^ Min [4] ^ Nin [1] ^ Nin [3]

Mout [4] = Min [0] ^ Min [3] ^ Nin [2]

Mout is the parallel CRC implementation.

USB CRC5 with N=4 the parallel CRC equations

PARALLELCRC

GENERATION

CRC REGISTER

DATA BUFFER

DATA*+

CRC

CRC CHECKER

DATA(7:0)

ERROR NO ERRORDATA(7:0)*

CRC

CRC

#1

PRECALCULATED

CRC

CRC REGISTER

DATA BUFFER

PARALLELCRC

GENERATOR

COMPARATOR

ERROR NO ERROR

DATA(7:0)CRC

CRC

CRC*

DATA(7:0)*

#2

PARALLELCRC

GENERATOR

CRC REGISTER

DATA BUFFER

PARALLELCRC

GENERATOR

COMPARATOR

ERROR NO ERROR

DATA(7:0)CRC

CRC*

CRC

DATA(7:0)*

#3

PARALLELCRC

GENERATOR

CRC REGISTER

DATA BUFFER

PARALLELCRC

GENERATOR

COMPARATOR

ERROR ‘1’

NO ERROR

0X1F0x8041

0X8261

0X8041

0XEF

Example based for #3

FPGA Data Width

Algorithm Logic Cells

Registers

LUT

Stratix EP10S1F672C6

16 CRC-16-USB

86 32 54

Stratix EP10S1F672C6

8 CRC-16-USB

22 16 6

Stratix EP10S1F672C6

8 CRC-16-USB

81 0 81

Results

Parallel/LUT CRC Generation Block

PARALLELCRC

GENERATION

CRC REGISTER

DATA BUFFER

DATA*+

CRC

CRC CHECKER

DATA(7:0)

ERROR NO ERRORDATA(7:0)*

CRCCRC

PARALLELCRC

GENERATOR

CRC REGISTER

DATA BUFFER

PARALLELCRC

GENERATOR

COMPARATOR

ERROR NO ERROR

DATA(7:0) CRC

CRC*

CRC

DATA(7:0)*

Comparison

References

[1] G. Campobello, G Patane, M Russo, “Parallel CRC Realization” (http://ai.unime.it/~gp/publications/full/tccrc.pdf)

[2] G.Albertango and R. Sisto, “Parallel CRC Generation”, IEEE Micro, Vol. 10, No. 5, October 1990, pp. 63-71.

[3] A. Perez, “Byte-wise CRC Calculations”, IEEE Micro, Vol. 3, No. 3, June 1983, pp. 40-50

[4] Adrian Simionescu, Nobug Consulting http://space.ednchina.com/upload/2008/8/27/5300b83c-43ea-459b-ad5c-4dc377310024.pdf

[5]Evgeni Stavinov, 2010 issue of Circuit Cellar magazine, Page 40.

[6] R. J. Glaise, “A two-step computation of cyclic redundancy code CRC-32 for ATM networks”, IBM Journal of Research and Development Volume 41 , Issue 6 (November 1997) pp 705 - 710

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