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8/13/2019 International Society 2010 2
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Noise reduction of TDC by using a GRO TDC and
a noise shaping structure Kazuya Kobayashi Yusuke Fukasawa Akira Yasuda
Engineering Research Course, Hosei
University3-7-2, Kajino-cho, Koganei-shi, Tokyo
184-8584, Japan
Engineering
Research Course,
Hosei University3-7-2, Kajino-cho,
Koganei-shi, Tokyo
184-8584, Japan
Engineering
Research Course,
Hosei University3-7-2, Kajino-cho,
Koganei-shi, Tokyo
184-8584, Japan Email: kazuya.kobayashi.fa@stu.hosei.ac.jp yasuda@hosei.ac.jp
Abstract In this paper, we propose a noise reduction
method for a time-to-digital converter (TDC) using a
first-order noise shaping structure and a gated ring
oscillator (GRO) TDC. The noise shaping structure is built
into delta-sigma modulations. Therefore, we convert the
structure of a TDC into a delta-sigma structure. The
proposed TDC requires a phase subtractor and a phase
integrator to subtract and integrate a phase, respectively.
A GRO TDC is used as a quantizer to prevent the addition
of a quantization error. The proposed TDC can reduce the
quantization error due to device mismatch. The SNR of
the proposed TDC is increased by 14 dB comparing to a
GRO TDC by 14 dB.
Keywords time-to-digital converter, gated ring
oscillator, noise shaping.
I. INTRODUCTION
A time-to-digital converter (TDC) is a device for converting
the width of an input pulse into a corresponding digital value. ATDC can measure the pulse interval of two signals. A TDC is
used in a digital phase locked loop (PLL) circuit and in certain
analog-to-digital converters (ADCs). A PLL plays the role of a
wireless communications system or a clock generation circuit
in a digital chip. The accuracy of a PLL can be increased by
reducing the jitter and lock-up time. One of the desired
improvements in a PLL performance is the quantization noise
reduction of a TDC that configures the PLL. An inverter delay
line (IDL) TDC and a vernier delay line (VDL) TDC are
high-resolution devices; however, this resolution is determined
by device technology. In this paper, we propose a noise
reduction method for a TDC using a gated ring oscillator
(GRO) TDC1)2) and a first-order noise shaping structure.
II. CONVENTIONAL METHOD
(1) Inverter Delay Line TDC
Fig.1 shows the circuit of an IDL TDC. The clock signal,
CLKA, is delayed by the delay inverter chain. The delayed
CLKA is connected to the input of the flip-flops controlled by
the CLKB. The IDL TDC converts the phase difference
between the CLKA and CLKB into a thermometer code. Theresolution of the phase difference depends on the delay time of
the inverter. The phase difference is the value of the output
thermometer code multiplied by the inverter delay time. The
number of inverters IDL N is given as
inv P IDL t T N , (1)
where P T is the maximum phase difference between two
signals andinvt is the inverter delay time. The resolution
depends on the process technology. Therefore, advancements
in the process technology are required for improving the IDL
TDC.
CLKA
CLKB
Q 0) Q n) n-1) 3) 2) 1)
Fig. 1 Inverter Delay Line TDC
(2) Vernier Delay Line (VDL) TDCFig.2 shows the circuit of a VDL
3) TDC. The VDL TDC has
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two delay buffer chains. The resolution of the VDL TDC can
be expressed as )( 21 t t , if 1t > 2t ; 1t and 2t are the
buffer delay times of the upper and lower delay chain,
respectively. The above expression implies that the VDL-TDC
enables a high-resolution detection. The combination of an
upper and lower buffer compose a vernier stage. The number
of the vernier stagesVDL N is given as
)( 21 t t T N P VDL , (2)
where P T is the maximum phase difference between the two
signals. The above equation indicates thatVDL
N depends on
P T . In other words, the circuit size increases with the P T .
The VDL TDC has a higher resolution than the IDL TDC
because, in case of the VDL-TDC, there is a delay difference
between the two delay buffers. However, the VDL TDC is a
larger circuit than the IDL TDC. The demerit of the IDL and
VDL TDC operations is the increase in the output error caused
by a device mismatch.
D
Q
t1
CLKA
CLKB
t1 t1
Q10 Qn
t2 t2 t2
D
Q
D
Q
Fig. 2 Vernier Delay Line TDC
(3) Gated Ring Oscillator (GRO) TDC
Fig.3 shows the circuit of a GRO TDC2). When the Enable
signal is high, the counters count the inverter outputs of the
GRO. This value is simultaneously saved by a register. The
counter resets the value when the Enable signal is low. Fig.4
shows the time chart of the behavior described above.
Noise is reduced by using a GRO as the loop structure
reduces the delay time error caused by device mismatch. The
advantage of using a GRO TDC is that the state at the end of an
Enable signal can be transferred to the beginning of the next
Enable signal. Let start T and stopT denote the times at the
beginning and end of the Enable signal. The relationship
between start T and stop
T is given as
]1[][ k T k T stop start . (3)
The quantization error at the end of the Enable signalerror
T
is
][][][ k T k T k T start stoperror . (4)
Thus,
]1[][][ k T k T k T stop stoperror (5)
][)1(][ 1 z T z z T stoperror
(6)
Because the next quantization error is subtracted from the
previous one, equation (5) represents first-order noise shaping.
Resister
Counters
+
Enable
OUT
Count
Reset
Gated Ring Oscillator
Fig. 3 Gated Ring Oscillator TDC
7
Enable
Oscillator
phases
Count
Out
Tstop [k ]
Tstart [k ]
Tstop [k ]
Tstart [k ]
Fig. 4 Time chart of the GRO TDC
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III. BASE CONFIGURATION OF THE PROPOSED TDC
Delta sigma modulation
Fig.5 shows the fundamental structure of the first-order deltasigma modulation. An input signal passes through the
integrator constructed by a delay block, which is quantized.
The quantized signal passes through a lower feedback path and
is subtracted from the input signal. Because the difference
between the input and quantized signals is a quantization error,
the error is integrated by the integrator. The transfer function of
the modulation shown in Fig.5 is
Q Z X Y )1( 1 , (6)
where X is the input; Y, the output; and Q, the quantizer error.
Equation (6) indicates that the input signal is outputted without
any change and the quantization error is reduced by first-order
noise shaping.
Z-1
QUANTIZER
Z-1
+
+
+
+
-
X
Q
Y
Fig. 5 Delta sigma modulation
IV. PROPOSED METHOD
We propose a method to reduce the output quantization noise
of the GRO TDC by using a delta sigma structure. However, a
simple integrator and subtractor cannot be used in the proposed
TDC; this is because the phase (or time) integration and
subtraction should be realized in time domain. Therefore, wefirst propose the subtraction circuit and then the integration
circuit. Finally, we discuss the complete circuit of the proposed
TDC.
(1) Phase Subtractor
Fig.6 shows the circuit of a phase subtractor. The phase
subtractor outputs the phase difference between the two pulses.
IN is an input pulse, and FB is the digital feedback having an
integer value. Therefore, the FB value should be converted to a
pulse corresponding to the digital value. FB is inputted into a
variable-time-delay circuit. This circuit delays IN when its
value corresponds to that of FB. Because IN and delayed IN
are inputted into S and R of an RS flip-flop, Q of the flip-flop
outputs the pulse width corresponding to FB. The pulse,
generated by comparing IN with Q, is the output of the phase
subtractor. The comparison corresponds with the phasesubtraction. OUT+ is high when IN is higher than Q; on the
other hand, OUT- is high when IN is lower than Q. These two
outputs of the phase subtractor express the positive and
negative phase difference. The time chart of the phase
subtractor is shown in Fig.7.
Fig. 6 Phase Subtractor
Fig. 7 Time chart of the Phase Subtractor
(2) Phase Integrator
The circuit of a phase integrator is shown in Fig.8. It is not
possible to integrate (or add) the phases. The input pulse IN is
delayed during the (1 + 1/n) cycles, where n denotes the
integration number. The next IN and delayed IN are inputted
into an OR gate. The delay time prevents the two signals from
overlapping. The OR operation corresponds with the phase
integration. The integration number n denotes the number of
pulses included in one cycle. The integration number depends
on the input pulse width. The reduction of the input pulse
results in an increase in the realized integration number. Fig.9
shows the time chart of the phase integrator.
Z-1
Z-1
Z-1
OUT
IN
Fig. 8 Phase Integrator
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Fig. 9 Phase Integrator (n = 5)
(3) Complete circuit of the Proposed TDC
Fig.10 shows the circuit of the proposed TDC. The basic
configuration of the proposed TDC is the delta sigma
modulation shown in Fig.5. The circuits of the quantizers,
subtractor, and integrators are shown in Fig.3, Fig.6, and Fig.8,
respectively.
Phase
Subtractor
Subtractor)
Phase
Integrator
Integrator)
GRO TDC
Quantizer)
GRO TDC
Quantizer)
0
1
n
+
+
Phase
Integrator
Integrator)
0
1
n
Fref
OUT
+
-
Fig. 10 Complete circuit of the proposed TDC.
The phase subtractor subtracts the output value OUT from the
input pulse In. Because the phase subtractor has OUT+ and
OUT-, the proposed TDC has two paths. The phase integrator
adds one input pulse to the delayed input pulses. The GRO
TDC converts the input pulses to a digital value. The digital
value enables the addition of the positive path value to the
negative path value.
Since the phase integrator outputs the multiple pulses shown
in Fig. 9, a counter adds the quantized pulses. If the counter
individually measures each pulse width, the quantization noise
caused by counting is summed up. This process degrades the
noise performance. The consequence is that the quantization
noise is added n times. Fig.11 shows the noise addition of a
counter. Using the GRO TDC as the counter prevents the
additional quantization noise caused by counting.
1cycle
IN
OUT
Q Q Q Q Q Q
Fig. 11 Noise Addition at a Counter
The gains, i, at the subsequent stage of the counters stabilize
the output. As shown in Fig.12, the longer the delayed input
pulse, the smaller the gain used. The pulse width of the first
input pulse of the phase integrator is large because the initial
value of the feedback inputted into the phase subtractor is zero.
The value of the output of the subtractor is normally small at a
steady state owing to the feedback principle. Since the
integration number is n, the (n+1)th output pulse of the phase
integrator does not include the first input pulse. The (n+1)th
output value of the counter is small. Thus, the phase subtractor
outputs a long pulse again because a small feedback value is
inputted into the phase subtractor. Repeating the above
behavior in (n+1) cycles provides an unstable circuit output.
The gains decrease the influence of the output that does not
include a long input pulse.
IN
OUT 1 0.8 0.2.4.6 1
1cycle
Fig. 12 Gain setting of n = 5
V. SIMULATION
The circuits were simulated using MATLAB/Simulink. Table
1 shows the simulation condition. The input pulse sequence
shows a pulse width modulated with a sinusoidal signal. In this
simulation, the integration number n is 10.
Tab. 1 Simulation condition
Input frequency 1 [Hz]
Input duty ratio 31~57%
Counter sampling frequency 100 [Hz]
Noise model 0.0123 [Hz]
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The output waveform of the proposed TDC without the gain ,
i, of the counter output is shown in Fig.13. The simulation
result shows that the output decreases periodically.
The output waveform of the proposed TDC with the gains i,is shown in Fig.14. Table 2 shows the gain setting. Fig.14
shows that the proposed TDC with the gains reduces the
periodic drop and stabilizes the output code.
Fig.13 Output Waveform without the Weighted Gains
Tab. 2 Gain setting
1a 1.0
6a 0.5
2a 0.97a 0.4
3a 0.8
8a 0.3
4a 0.79a 0.2
5a 0.6
10a 0.1
Fig. 14 Output Waveform with Weighted Gains for Counter
Output
The output FFTs of the GRO TDC and the proposed TDC is
shown in Fig.15 and Fig.16, respectively. Fig.15 and Fig.16
show first-order and more aggressive first-order noise shaping,
respectively. The signal-to-noise ratio (SNR) of the GRO TDC
and proposed TDC is 84.3 dB and 98.4 dB, respectively. The
SNR is improved by approximately 14 dB in case of the proposed TDC.
The SNR depends on the integration number n. As the
integration number is 10, the SNR must be improved by 20 dB.
However, the gains after the counters convert the gain of
integrator from 10 times to 5.5 times. As a result, the SNR is
improved by 14 dB in case of the proposed TDC.
Fig.15 Output Spectrum of GRO TDC
Fig. 16 Output Spectrum of the Proposed TDC
VI. CONCLUSIONS
In this paper, we propose a method for improving the TDC
resolution and reducing the nonlinearity error caused by a
nonideality such as a device mismatch. The proposed TDC
involves the use of a GRO TDC along with a noise shaping
technique. The SNR can be improved by increasing the
integration number n. The proposed TDC can be used in
high-precision applications such as PLLs and high-speed
ADCs.
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VII. REFERENCES
1) Matthew Z. Straayer, Michael H. Perrott: A 12-Bit,
10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a
5-Bit, 950-MS/s VCO-Based Quantizer, IEEE Journal ofSolid-State Circuits, Vol.43, No.4 APRIL 2008, pp.
805-814.
2) Matthew Z. Straayer, Michael H. Perrott: A Multi-Path
Gated Ring Oscillator TDC With First-Order Noise
Shaping, IEEE journal of Solid-State Circuits, Vol.44,
No.4 APRIL 2009, pp.1089-1098.
3) Piotr Dudek, Stanislaw Szxzepanski, John V. Hatfield: A
High-Resolution CMOS Time-to-Digital Converter
Utilizing a Vernier Delay Line, IEEE Transactions on
Solid-State Circuits, Vol.35, No.2, FEBRUARY 2000, pp.
240-247.
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