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Integrated Circuit Design ELCT 701 (W19)
Lecture 8: Design of Sequential
Logic Circuits (1)Dr. Eman Azab
Assistant Professor
Office: C3.315
E-mail: eman.azab@guc.edu.eg
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
1
Sequential LogicDesign Concept
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
2
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
3
COMBINATIONALLOGIC
Registers
Outputs
Next state
CLK
Q D
Current State
Inputs
Introduction Sequential logic circuits are different from the
combinational ones because they have memory
logic value can be stored using:
Positive feedback (Static)
charge storage (Dynamic)
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
4 Introduction In the following slides we will take the following
assumptions:
A latch is level sensitive
Negative Latch is transparent when CLK=0
Positive Latch is transparent when CLK=1
A register is edge-triggered
Clk
D Q
tC 2 Q
Clk
D Q
tC 2 Q
tD 2 Q
Register Latch
Static Sequential LogicDesign Concept
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
5
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
6 Static Sequential circuits Positive Feedback Circuits
Bi-stable Circuits
There is only two stable points (A & B)
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
7 Static Sequential circuits Positive Feedback Circuits
Bi-stable Circuits
Point C is a metastable point
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
8 Static Sequential circuits Positive Feedback Circuits
1. Multiplexer based Static Sequential Circuits
• Multiplexer based Latch
InClkQClkQ
InClkQClkQ Negative Latch
Positive Latch
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
9 Static Sequential circuits Positive Feedback Circuits
1. Multiplexer based Static Sequential Circuits
• Multiplexer based Latch using TGs
CLK
CLK
CLK
D
Q
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
10 Static Sequential circuits Positive Feedback Circuits
1. Multiplexer based Static Sequential Circuits
• Latches using NMOS switch and Non-overlapping
clocks
CLK
CLK
CLK
CLK
QM
QMD
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
11 Static Sequential circuits Positive Feedback Circuits
1. Multiplexer based Static Sequential Circuits
• Registers using Master-Slave (Positive & Negative) Latches
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
12 Static Sequential circuits Positive Feedback Circuits
1. Multiplexer based Static Sequential Circuits
• Registers using Master-Slave (Positive & Negative) Latches (TGs)
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
13 Static Sequential circuits Positive Feedback Circuits
2. Writing data by Pure Force
• Static SR flip-flops (NOR based)
Forbidden State
S
S
R
Q
Q
Q
QRS Q
Q00 Q
101 0
010 1
011 0RQ
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
14 Static Sequential circuits Positive Feedback Circuits
2. Writing data by Pure Force
• Static SR flip-flops (NAND based) optimized design
• Careful transistor sizing?
M1
M2
M3
M4
Q
M5S
M6CLK
M7 R
M8 CLK
VDD
QAdded clock
Dynamic Sequential
LogicDesign Concept
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
15
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
16 Dynamic Sequential circuits Charge storing Circuits
• Difference between Static and Dynamic sequential
logic
D
CLK
CLK
Q
Dynamic (charge-based)
CLK
CLK
CLK
D
Q
Static
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
17 Dynamic Sequential circuits Charge storing Circuits
1. Dynamic TG edge-triggered Register
• Problem with clock overlapping (clock Skew)
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
18 Dynamic Sequential circuits Charge storing Circuits
2. C2MOS Register
• Clock-skew insensitive approach
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
Slave Stage
“Keepers” can be added to make circuit pseudo-
static
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
19 Dynamic Sequential circuits Charge storing Circuits
2. C2MOS Register
• Clock-skew insensitive approach
M1
D Q
M4
M2
0 0
VDD
X
M5
M8
M6
VDD
(a) (0-0) overlap
M3
M1
D Q
M2
1
VDD
X
M71
M5
M6
VDD(b) (1-1) overlap
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
20 Dynamic Sequential circuits Charge storing Circuits
3. True Single-phase Clocked Register (TSPCR)
• Clock-skew insensitive approach with one clock
signal only (no complement in needed)
CLKIn
VDD
CLK
VDD
In
Out
CLK
VDD
CLK
VDD
Out
Negative latch(transparent
when CLK= 0)
Positive latch(transparent when
CLK= 1)
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
21 Dynamic Sequential circuits Charge storing Circuits
3. True Single-phase Clocked Register (TSPCR)
• Advantage: adding Combinational logic in-
between!
CLKIn CLK
VDDVDD
Q
PUN
PDN
CLK
VDD
Q
CLK
VDD
In1
In1 In2
In2
AND latchExample: logic inside the latch
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
22 Dynamic Sequential circuits Charge storing Circuits
3. True Single-phase Clocked Register (TSPCR)
• Simplified Circuit
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