Homework 1 EE 240b Advanced Analog Circuits

1UNIVERSITY OF CALIFORNIA

College of Engineering

Department of Electrical Engineering and Computer Sciences

Lingkai Kong Homework 1 EECS 240Due Thursday, Feb. 7th 2013

Use the EECS 45nm GPDK design kit in all homework and projects unless otherwise noted.The setup of Cadence as well as the PDK can be found on the course website.

1. This problem reviews some of the basic analysis you have learned in EE140 or its equivalent. Pleaseanalyze the simple amplifier design shown below with the assumption that the small signal outputimpedance (ro) is infinity.

Vin

VoutRS

RF

R1 C1

Figure 1: Schematic of problem 1

(a) Draw the small signal model of the above circuit. For simplicity, you can include only Cgsand set both Cd and Cds to be zero.

(b) As a function of the transistors transconductance gm and resistors RS , RF and R1, what isthe DC small signal gain of this amplifier (Vout/Vin)?

(c) Calculate the AC response of the amplifier and sketch the Bode plot of Vout/Vin. You need tolable the positions of poles and zeros and the corresponding magitude of the transfer function.

2. In this problem we will look at the design of MOM capacitors in our 9-layer metal process. Unlessotherwise noted, you should assume that all metal layers have a thickness T = 200nm, minimumwidth W = 100nm, minimum horizontal spacing S = 100nm, vertical spacing H = 200nm, andthat the insulator is SiO2 (r = 3.9). You can assume that the separation of the lowest layer ofmetal from the substrate is also H = 200nm, and that the inter-layer vias have the same widthas the wires they are connected to. For simplicity, you can ignore fringing fields in all of thesecalculations.

(a) What is the maximum capacitance density (in fF/m2) you can achieve with horizontalparallel plate? What is the ratio of capacitance to bottom plate parasitic?

(b) What is the maximum capacitance density (in fF/m2) you can achieve with vertical parallelplate? You can assume you are able to build a via wall without any spacing between vias.Now what is the ratio of capacitance to bottom plate parasitic?

(c) In both cases, removing bottom layers can reduce the bottom plate parasitic at the cost oflower capacitance density. Plot the ratio of the bottom plate parasitic to the capacitanceversus the capcitance density.

23. In this problem you will need to run BAG or Spectre/HSPICE (or whatever your favorite simulatoris). For some of the problems you should access internal device parameters such as gm or Vth. Ifyou do not know how to do that, please come to the discussion session. If you are using BAG,please refer to the BAG tutorial for the syntax.For this problem, you should plot the results for all of the process corners provided in the library(i.e. SS, TT, FF). Unless otherwise specified, use minimum length transistors with W = 1m anda maximum |Vgs| and |Vds| of 1.0V.

(a) Plot the magnitude of the threshold voltage of an NMOS and PMOS transistor as a functionof the channel length L. You should sweep L from 50nm to 500nm be sure to use a step sizesmall enough to measure a smooth curve.

(b) Plot the gm versus Vgs of an NMOS on a linear AND log scale, biasing the transistor withVgs = Vds.

(c) Plot gm/Ids as a function of |Vgs| (still with Vgs = Vds) for an NMOS AND PMOS withL=50nm, 100nm, 150nm, and 200nm.

(d) Use the data from part (c) to plot V = 2Ids/gm as a function of |Vgs|.

(e) Using the data from part (c), plot Ids as a function of V .

(f) Plot the output resistance ro and DC gain gmro versus Vds for an NMOS and PMOS. Youshould bias the transistors with V = 200mV . What is the allowed output swing to maintaina DC gain of 80% of the peak value? If you are not sure how to set up this simulation, pleasecome to the disscussion session as well.

(g) Plot fT and fT (gm/Ids) as a function of |VgsVth| for L=50nm, 100nm, 150nm, and 200nm.You should set Vgs = Vds and vary |VgsVth| from 0 to 500mV. What is the V that achievesthe maximum fT (gm/Ids) for each channel length?