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High-Speed Serial Link Design for Signal IntegrityRishi RatanSignal Integrity Research Group | Advisor: Prof. José E. Schutt-Ainé
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
April 11, 2014
OUTLINE
1. Motivation
2. High-Speed Links
Serial vs. Parallel Links
Basic Serial Link Architecture
3. Serial Link Building Blocks
Transmitter
Clock Synthesizer
Channel
Equalization
Receiver
Timing Recovery
4. High-Speed IO Links FOM (Figures of Merit)
BER (Bit-Error Rate)
ISI (Intersymbol Interference)
Crosstalk
Jitter
5. Signal Integrity Issues
6. Simulation Tools Overview
Motivation
Advances in SFT (Semiconductor Fabrication Technology), innovations in IC scaling have fueled an unparalleled growth in computing.
Faster data-rates and higher processing power needed in everyday computing devices: data-center servers, PCs and mobile devices.
Desire for robust, high-speed, low-power and highly integrable compact SOCs paramount for inter-IC communication interfaces.
Network switches, memory/processor across backplane channels
Limited channel BW, microwave effects at high data-rates SI Issues
Serial vs. Parallel Links
High-Speed Links Overview
Traditional parallel communication not suitable for inter-IC data transport in high-speed data links.
Heavy design overheads and due to crosstalk, clock-skew effects and high IO pin count.
As supply voltages have scaled down, legacy parallel bus voltages have not thus making them incompatible with modern processes.
Parallel communication still used amongst internal buses of ICs thus cannot be eliminated entirely.
Solution: SerDes (“Sir-Deez”)
Use serial links for inter-IC communication and parallel links for intra-IC communication.
Serial links occupy smaller area, have fewer IO pins lower packaging cost and don’t suffer from clock-skew problems!
Widespread usage in industry for links with data-rates > 2Gbps.
Inter-IC Communication Trends
High-Speed Links Overview
Basic Serial Link Architecture-I
TX: Generates train of analog pulses depending upon input digital data symbols and transmits them across the channel to the receiver.
Channel: Electrical path between TX and RX blocks. Typically comprises of PCB traces, vias, connectors and other such I/O interface components.
RX: Amplifies the recovered analog signal and samples it to output the corresponding digital bitstream.
Timing Recovery: Circuit block responsible for deciding the correct sampling strobe point to sample and convert received data from analog to digital.
High-Speed Links Overview
Basic Serial Link Architecture-II
Serializer: converts input parallel data-bits into serial for inter-IC transmission across lossy channel.
PLL: Phase-locked loop used as a clock-synthesizer circuit that generates the high-speed master clock used for data transmission.
CDR: Clock-Data Recovery circuit that performs the timing recovery function to recover TX clock to sample the received signal at the RX.
Deserializer: converts recovered data-bits from serial to parallel form.
High-Speed Links Overview
Single-Ended vs. Differential Signaling
Current Mode vs. Voltage Mode Drivers
Clock Synthesizer
PLL based clock-generating circuit needed to have a high-speed system master clock at the TX side.
Reference clock generated by piezoelectric crystal but can only produce a stable, low-jitter clock in the MHz range.
Basic Idea: take the reference signal and generate a scaled up clock at a higher frequency by eliminating static phase errors using a negative feedback control system in form of PLL.
Serial Link Building Blocks
IN
÷N
ICP
DIV
REF
OUT
VCO
PFD CP LFVCTRL
Channel
Serial Link Building Blocks
Equalization
Serial Link Building Blocks
Goal: Counteract the channel degradation by trying to flatten the frequency response on both TX as well as RX fronts to remove time-domain ISI effects.
Eye-Diagrams
High-Speed I/O Links FOM (Figures of Merit)
Timing Recovery
Serial Link Building Blocks
BER (Bit-Error Rate)
High-Speed I/O Links FOM (Figures of Merit)
Typically between 10−12 and 10−15 for modern High-Speed links.
Ratio of the number of erroneous bits received and the total number of bits transmitted. Number of bit errors per second.
Most significant metric for link characterization.
Estimation of BER is fundamental challenge for link designers:
Impractical to simulate the link with sequence of 1012 bits when trying to accurately predict system BER.
Measurement possible using a BERT once chip is fabricated but that is typically too late to make necessary design changes.
Statistical means to estimate by collectively take into account effects of ISI, supply/substrate-noise, timing jitter and other noise sources is only feasible means.
Timing Margin
𝑡𝑚𝑎𝑟𝑔𝑖𝑛 = 𝑡𝑏𝑖𝑡 − 𝑡𝑜𝑠 − 𝑡𝑗𝑑 − 𝑡𝑗𝑐
Where,
𝑡𝑏𝑖𝑡 = bit-width of a symbol
𝑡𝑜𝑠 = sampling error
𝑡𝑗𝑑/𝑡𝑗𝑐 = data/clock jitter
High-Speed I/O Links FOM (Figures of Merit)
ISI (Intersymbol Interference)
High-Speed I/O Links FOM (Figures of Merit)
Form of signal distortion that is caused due to:
Reflections
Channel resonances
Channel loss/dispersion
Interference between symbols wherein current bit/symbol can cause distortion in its subsequent/preceding bit/symbol.
Crosstalk
High-Speed I/O Links FOM (Figures of Merit)
Short traces in connectors/vias suffer from impedance mismatches that cause reflections and lead to inter-channel interference called crosstalk.
Mainly caused by capacitive or inductive coupling between multiple signal lines and is severe predominantly at low frequencies.
Two prominent types:
NEXT: XT due to energy dissipated from coupling between transmitted signal and the reflected signal on the same chip.
FEXT: XT due to energy dissipated from coupling between transmitted signals of two different chips.
NEXT worse than FEXT!
Timing Jitter
High-Speed I/O Links FOM (Figures of Merit)
Jitter = time-domain variation in clocksignal. Dominated by power-supply noiseand substrate noise both of which don’tscale with technology.
Signal Integrity Issues in Serial Link Design
Channel BW is biggest design bottleneck!
Stochastic modeling of substrate
ISI and crosstalk issues in the channel
Simulation Environment for High-Speed Links
Use Cadence Virtuoso for transistor level modeling and design of link blocks like TX driver, RX driver as well as the clocking circuits.
Model the channel in Ansys HFSS and extract the S-parameter data to import it back into Virtuoso for full link simulation.
Characterize link-performance by simulating the timing jitter as well as transient noise-profile within Virtuoso.
Plot the eye-diagram at output of TX as well as output of channel to calculate the voltage margin and timing margin.
In MATLAB, write a script to calculate the “worst-case” eye and estimate the BER performance of the link.
Consider using CppSim simulator for system level modeling of the timing recovery circuit in order to accurately construct the transistor level model in Virtuoso.
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