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1
Term Project
EE619
High-Performance Full Adders Using
an Alternative Logic Structure
by
Atulya Shivam Shree (10327172)
Raghav Gupta (10327553)
Department of Electrical Engineering, Indian Institure Technology, Kanpur.
Jan-Apr ‘14.
2
Contents
1. Introduction 3
2. CPL Full adders 4
3. SR-CPL & DPL style Full adders 5
4. Layout of cells 6
5. Simulations 8
6. Results 9
7. Conclusions 12
8. References 12
3
Introduction
As technology improves there is always demand for low power electronic
systems that can be used in portable applications to preserve battery life. Along
with low power there is also a requirement for high speeds so as to be able to
operate at higher frequencies efficiently. Unfortunately, to reduce the power of
a circuit one must usually compromise on its speed, since lower power translates
into smaller current which would ultimately lead to a slower circuit. As a result
a useful metric used in such cases is the Power Delay Product (PDP) which can
be used to characterise the overall performance of a system. The PDP can be
improved at various levels- device level, layout level, circuit level, architectural
level. Here circuit level enhancement of PDP is examined.
Addition is a very fundamental arithmetic operation and as a result adders are
widely used in arithmetic circuits including multipliers and (Arithmetic Logic
Unit) where they form the key cells of the design. Full adders are the building
blocks of various applications of VLSI, digital signal processing, microprocessors
and image processing.
In this project two new low power and low delay designs for the full adder are
examined. These designs are based on the Double Pass Transistor Logic (DPL)
and Swing Restored Complementary Pass Transistor Logic (SR-CPL) styles. The
basic structure of the adder used is as follows:
Fig. 1 – Alternative Logic scheme for Full Adders [1]
As can be seen from the truth table of the adder, So = when Cin = 1 and
when C=0. Also, Co = when Cin = 0 and when Cin = 1.
4
CPL Full Adder
The Complementary Pass Transistor Logic style is a well-known low power logic
style. The CPL style uses NMOS pass transistors to implement logic and
eliminates the PMOS transistors completely. The use positive feedback and
NMOS transistors only makes the circuit naturally fast. Hence the transistors can
also be made small without much compromise on speed. The CPL style full
adders generate both carry and sum outputs along with their complements. The
use of complementary inputs along with generating complementary outputs
makes the transistor count for this design larger as compared to other designs
but the drivability of the circuit is good due to the use of pull up PMOS
transistors to restore swing. Hence output inverters need only be used after
alternate stages and when used in larger circuits complementary inputs might
be available thereby reducing transistor count. Thus, a standard CPL style full
adder is used as a benchmark to compare the two new designs in terms of
power, delay and PDP. The design of the adder used is as shown in Fig 2.
Fig. 2 - CPL Full Adder [2]
5
SR-CPL & DPL style Full adders
Two new designs based on SR-CPL and DPL style full adders are being examined
in this project. The main advantages of this design are:
Multiplexers are directly controlled by Cin instead of internally generated
signals thereby reducing delay.
Capacitive load on Cin is reduced
The propagation delay of So and Co can be tuned by sizing XOR/XNOR
gates appropriately
The inclusion of buffer at input can be integrated by using NAND/NOR
gates instead of XOR/XNOR gates
The designs being examined in this project are shown in Fig 3.
a) Design 1 (D1) b) Design 2 (D2)
Fig. 3. Designs being examined- D1 & D2
6
Layout of Cells
Fig 4. Design 1 Layout
Fig 5. Design 2 Layout
7
Fig. 6. CPL Adder Layout
Design 1 Design 2 CPL Adder
Area (μm2) – our layout 116 118 238
Area (μm2) – from [1] 246 243 378
8
Simulations The test bed used for the simulation is as follows:
Fig 7. Test bed for simulations
Buffers are placed at the inputs are placed to account for the load the device
offers at the inputs. Also, since the designs presented here consist of pass
transistor logic which has no direct power supply connection, the power
consumed by the device also comes through these inverters. The output
inverters account for the power due to degraded voltage swing and slopes of
full adder output.
The full adders have been simulated using 180-nm CMOS technology using
Mentor Graphics. The model used for the simulations was tscm018 and post
layout extracted R and C parasitics were included during simulations. The value
of supply voltage VDD used was 1.8V.
Fig 8. Sample Output
9
Results
Current Dissipation Transitions Design 1 (D1) Design 2 (D2) Reference (CPL)
A 010, B=0, Cin =1 32.6u 32.5u 47.2u
A 010, B=1, Cin =0 32.1u 31.4u 47.4u
B=010,A =0, Cin =1 32.5u 31.3u 45.2u B 010, A=1, Cin=0 35.5u 32.7u 45.4u
Cin 010, A=0, B=1 27.7u 24.7u 45.2u Cin 010, A=1, B=0 31.0u 25.1u 45.2u
1 The frequency used for the simulations is- 200MHz 2 The supply voltage used was 1.8V
Delay Transitions Design 1 (D1) Design 2 (D2) Reference (CPL)
A 010, B=0, Cin =1 361.2p 239.2p 330.2p A 010, B=1, Cin =0 391.7p 241.2p 304.2p
B 010,A =0, Cin =1 386.6p 240.8p 288.8p B 010, A=1, Cin=0 383.1p 229.4p 322.3p
Cin 010, A=0, B=1 329.8p 205.6p 299.4p
Cin 010, A=1, B=0 368.1p 188.5p 313.2p 1 Only the worst case delays have been reported
Power Delay Product Transitions Design 1 (D1) Design 2 (D2) Reference (CPL)
A 010, B=0, Cin =1 21.2 13.9 28.1
A 010, B=1, Cin =0 22.6 13.6 25.9
B=010,A =0, Cin =1 22.6 13.5 23.6
B 010, A=1, Cin=0 24.5 13.5 26.3
Cin 010, A=0, B=1 16.5 9.2 24.5
Cin 010, A=1, B=0 20.5 8.5 25.5
1 PDP is in μW*ns
10
11
12
Conclusions We have presented three designs: D1 and D2 using alternative logic structure
and SR-CPL+DPL Logic style, and CPL style adder. The key features observed
were:
1. The proposed designs reduce both total average power and worst case
delay of the circuit. Total average power reduction of about 30-38% is
observed for D1 and about 27-45% for D2
2. Delay of D1 is comparable to that of the CPL logic (it is slightly greater for
most transitions). Delay of D2 is significantly smaller as compared to the
reference CPL Design – from about 16% to 31%
3. The overall Power delay product of both the designs is reduced as
compared to the standard CPL design ranging from about 5% to 25% for
D1 and about 43% to 66% for D2
4. The designs are more efficient both power wise and delay wise as
compared to the standard CPL design used
5. The transistor count for the proposed designs is also much less as
compared to the s CPL adder (26 & 28 as compared to 38)
6. The proposed designs occupy much less area as compared to the CPL
adder (116 μm2 & 118 μm2 for D1 and D2 vs 238 μm2 for CPL adder)
References 1. Aguirre-Hernandez, Mariano, and Monico Linares-Aranda. "CMOS full-
adders for energy-efficient arithmetic applications." Very Large Scale
Integration (VLSI) Systems, IEEE Transactions on 19.4 (2011): 718-721.
2. Quintana, J. M., et al. "Low-power logic styles for full-adder
circuits."Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE
International Conference on. Vol. 3. IEEE, 2001
3. J Rabaey, A Chandrakasan, and B Nikolic, Digital Integrated Circuits: A
Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 2003
4. Vijay, V., J. Prathiba, and S. Niranjan Reddy. "A REVIEW OF THE 0.09 µm
STANDARD FULL ADDERS." International Journal of VLSI Design &
Communication Systems 3.3 (2012)
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