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12/17/2009 www.kythuatvitinh.com 2
IEEE1394
TSB43AB23
DDR400
L0_CADOUT_H/L[15;0]
L0_CADIN_H/L[15;0]
L0_CLKOUT_H/L[1;0]
L0_CLKIN_H/L[1;0]
L0_CTLOUT_H/L[1;0]
L0_CTLIN_H/L[1;0]
HTTSTOP_L
CPUCLK0_H/L
SPI
BIOS
OUT
IN
+/-DC
LK[11;0]
-PWRBTSW / PSIN
VCC12_HTHT_12BVTTDDR25VSTRVCORE
VCC12_HT
VCC121P2VPLL_PWR
2P5V_PWR
VCC3AD[0;31]
CONTROL SIGL
VCC3
3VDUAL
RTCVDD
VCC15_DUAL
VCC15
VCC12
VCC-CPURST
CPU_PWRGD
MCP51
VDDA25CPUREF
HTMCP_UP[0;7]-HTMCP_UP[0;7]
HTMCP_DWN[0;7]-HTMCP_DWN[0;7]
HTMCP_UPCLK0-HTMCP_UPCLK0
-HTMCP_DWNCLK0HTMCP_DWNCLK0
HTMCP_UPCNTL-HTMCP_UPCNTL
HTMCP_DWNCNTL-HTMCP_DWNCNTL
VGA
PCI_EX1
PCI_EX16
THERMTRIP_CPU_L
SB_PWOK
PWOK
27 MHz
-PS
OU
T
W83303AG -IO_PSON
-ATX
_PSO
N
SMBDATASMBCLK
F_PANEL
-HTMCP_RST-HTMCP_PWRGD
25MHZ
MCPOUT_25MHZ
-HT_S
TOP
#
-H
T_STO
P#
MCPOUT_200MHZ-MCPOUT_200MHZ
-HT_REQ#
ATX MCP51
AMD K8
AM2C51G
MARVELL
88E1116
ITE
8716GB/CXALC883
-ACZ_RST
-PPCIRST-1394RST-IDERST
-LPCRST-BIOSRST
-TPMRST
-M
II_RST
PCICLK1PCICLK
2PCICLK3PCICLK41394CLKLPC33LPC24
ROMCLK33TPMCLK3397CLK14
CK8_PWOK
MEM_SMBDATA
MEM_SMBDATA
-SLP_S3
-SLP_S3
See page 20
HT1_VLDCPU_VL
DMEM_VLDHT1VDD_E
NCPUVDD_EN
LAD[0;3]
CTRL SIGL
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25 MHz
HT
HT
HT
HT
HT
HT
OTHER PLLS
OTHER PLLS
C51G
MCP51
AMD K8
AM2
200 MHz
200 MHz
200 MHz
25 MHz
200 MHzGA-M55plus-S3G Introduction
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MARVELL
88E1116
ALC
883
IEEE1394
TSB43AB23
SPI BIOS
ITE
8716GB/CX
IDE
PCI SLOT
PCI_EX16
PCI_EX1
MCP51
C51GAMD K8
AM2
ATX
SB_PWOK
CIRCUIT
SB_PWOK
PWRGDSLP_S3#
HTMCP_PWRGD
HTMCP_RST#
PS ONPWOK
1394RST#MII_RST# ACZ_RST#
PPCIRST#_SLOT1PPCIRST#_SLOT2PPCIRST#_SLOT3PPCIRST#_SLOT4
HT_CPU_PWRGD
HT_CPU_RST#
LPCRST_SIO# LPCRST_FLASH#IDERST#
PCIE_RST#
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ATX
Power SupplyPS ON#
PS ON#-PWRBTSW
PW
RB
TSW
SLP_S
3
PSIN
IT8716
nVIDIA
MCP51
5VSBSystem
On-Off
Button
5VSB→5VDUAL3VDUAL
-RSMRST
3VDUAL
RTCVDD
-RTCRST
VBAT
32.768KHZ
W83303AD
W83303AD
2N7002
S5_EN
SB_PWOK
See page 35
ADVANCED ACPI CONTROLLER
25.00MHZ
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14
VCORE
FET
SB_PWOK
ATX power
AM2
IT8716 GB/CXPower button
C51G
MCP51
-PWRBTSW
PWOKCK8_PWOK
-PS
OU
T
CPUPWROK
-CPURST
5VSB
5VD
UA
L
-RSMRST
FET
1
4
-SLP_S3
PWM
CPUVDD_EN
12
26
S5_EN
Circuit
3VDUALW83303AG FET
S5_EN
-SLP_S5
SB_PWOK Circuit
W83303AG
CPU_VLD
VCO
RE_PW
OK
HTMCP_PWRGD
HTMCP_RST#
-IO_PSON -ATX_PSON
MEM_VLD
VID
HT
VREG
HT1VDD_EN
HT1_VLD
5
6
7
9
10
118
Core Power Planes
13
19
2021
CPUCLK0_H/L-LP
CR
ST
2324
25
23
16
VCC12VCC15
2P5V_PWR
DDR18VDDRVTT
VCORE
DDR18V DDRVTT
VCC12_HT
VCC12_HT 20
VDDA25
VCC12 VCC12_HT
2P5V_PWR VCC3
VCC3 VCC15 VCC15_DUAL
VCC VCC12 VCC
VDDA25
VDDA
CIRCUIT
VDD
A25_EN
VDDA
CIRCUIT
VD
DA
25
AM2
18
2218
17
15
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CPU
CPU
CIRCUIT TSM104
CIRCUIT
FET
HT1VDD_EN
HT1_EN
HT1_VLD
VCC12_HT
PWMCPUVDD_EN VCORE
CPU_VLD
VCC
TSM104CIRCUIT CIRCUITVDDA25
MCP51(S-B)
Dual Diode
Dual Diode
VCOR_PWOK
VDDA25_EN
CPU,C51G
K8 Power Sequence
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POWER-UP SEQUENCE
+3.0V_VBAT
+5V_DUAL+3.3V_DUAL+1.5V_DUAL
25MHz xtal
PWRGD_SB
+2.5V_SUS+1.25V_VTT_SUS
COREPowerPlanes
SUSCLK(32KHz)
CPUVDD_EN
CPU_VLD
HTVDD_EN
+12V_HT
SLP_S5#
MEM_VLD
SLP_S3#
PWRGD
CPU_CLKLPC_CLK
+V_CPU
HT_VLD
LPC_PD#
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Power Sequence Timing
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BAT3.3V
5VSB
VCC3
VCC
+12V
+12V
DUALFET
FET AM2 CPU
3 phase vcore AM2 CPU
RTCVDD MCP51
VBAT IT8716F+
3.3V C51G
5VSB
VCC12
12V GD75232 PCI TSM104LM358DR
SOUND/CQ4
ATX P
OW
ER
CO
NN
EC
TOR
ATXBATTER
Y
DUALFET
AM2 CPU
DUALFET
3VDUALFETMCP51
W83310DG IEEE1394
W83303AGPCIE_1PCIE_16X
LAN/PCI
BIOS
FET VCC151.5V
VCC12_HT1.2.V
VDDA252.5.V
2P5V_PWR
FET VCC15_DUAL
5VDUAL FET DDR18V W83320G DDR2 AM2 CPUDDRVTT
MCP51
C51G
C51G
MCP51 IT6716F ALC883 W83303 DDR2 PCI
MCP51 IT8716F ISL6566 W83303 W83320 IEEE1394 PCI/GD7523
2
IT8716F W83303AG
PCIE_16X PCIE_1X
DUALFET C51G
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C51 Power Sequencing
POWER
SUPPLY
CPU
VREG
HT
VREG
MEM
VREG
AMD K8
AM2
C51G
MCP51PWRGDSLP_S3#
HT_CPU_PWRGD HT_CPU_STOP#
HTMCP_PWRGD HTMCP_RST#
VID
HT_VLD
HT_VDD_EN
MEM_VLD
SLP_S5#
CPU_VDD_EN
SB_PWOK
CPU_VLD
12/17/2009 www.kythuatvitinh.com 12
AMD K8
AM2
C51G/MCP51 Power Sequencing Block Diagram
C51G
MCP51
ROM
PCIRST#HT_VDD_EN
CPU_VDD_ENSLP_S3#SLP_S5#
LPC_PD#
HT_VLD
CPU_VLDMEM_VLD
SB_PWOKCK8_PWOK
HT_STO
P#H
T_REQ
#
HT_M
CP_PW
RG
D
HT_M
CP_R
ST#
HT_M
CP_D
N
HT_M
CP_U
P
HT_C
PU_D
N
HT_C
PU_U
P
HT_C
PU_R
ST#
HT_C
PU_PW
RG
D
CPU
_CLK
PRSNT#PERST#
PE_REFCLK#
CR
_REF_C
LK
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Clock Block Diagram
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CPU Power Supply Interface Signals
Signal Voltage Definition Remark
VCORE (VDD) 1.5V Core power supply
VCC12_HT/HT12B
(VLDT_A)
1.2V Hyper Transport I/O ring power supplies
VDD25 (VDDA) 2.5V Filtered PLL Supply Voltage
DDR18V(VDDIO)
1.8V DDR SDRAM I/O ring power supply
DDRVTT (VTT) 0.9V VTT Regulator voltage
CPU_M_VREF
(M_VREF)
VREF DRAM Interface Voltage Reference
COREFB_H/L
(VDD_FB_H/L)
A Differential feedback for VDD Power Supply
12/17/2009 www.kythuatvitinh.com 15
C51XE Power Supply Interface Signals
Signal Voltage Definition Remark
VCC12 (+1.2V_CORE)
1.6V Core Power Rail ,this power plane is for the C51G core
VCC12_HT
(+1.2V_HT)
1.2V Isolated Hyper Transport power rail
2P5V_PWR
(+2.5V_CORE)
2.5V 2.5V Core Power, this voltage is used to power the core logic of the C51G
1P2VPLL_PWR
(+12V_PLL)
1.2V +1.2V Voltage, this is a filtered version of the +1.2V_ core
voltage.1P2VPEA_PWR
(+12V_PEA)
1.2V +1.2V Voltage, provides power to the PCI Express integrated into the C51G
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MCP55P Power Supply Interface Signals
Signal Voltage Definition Remark
RTCVDD (+3.3V_VBAT)
3.3V RTC Power well ,Battery backed-up power plane on the onboard Real Time Clock.
+5V_DUAL 5 V Dual System Supply, The +5V_SB supply powers this rail in low power status and the +5V supply powers this rail during normal operation .
+3.3V_DUAL 3.3 V Dual Pad Supply, The +5V_dual supply powers this rail in low power status and the +3V supply powers this rail during normal operation .
VCC15_DUAL
(+1.2V_DUAL)
1.6 V Dual Logic Supply, Power plane for the logic in the MCP51 that remains active in all system status .
VCC12 (+1.2V) (+1.2V_HT)
1.6V VCORE Logic Supply, Power plane for the core logic in MCP51 , also potentially used for Hyper Transport pad power.
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Signal I/O Definition Remark
MEM_VLD# I Memory +2.5 V Power Valid
This signal indicates that the DDR DRAM +1.8 V power plane is valid.
CPUVDD_EN O CPU VDD Enable This signal controls the voltage regulator controlling the CPU_VDD power plane.
CPU_VLD# I CPU VDD Power Valid
This signal indicates that the CPU VDD power plane is valid.
HT1VDD_EN O Hyper Transport Link +1.2V_HT Enable
This signal controls the voltage regulator controlling the +1.2V_HT power plane.
HT1_VLD# I Hyper Transport Link +1.2 V Power Valid
This signal indicates that the +1.2V_HT power plane is valid.
AMD K8 AM2 Power Sequencing Signals
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