FPGA Calculator Core

Project CharacterizationChen ZukermanLiran Moskovitch

Advisor : Moshe Porian

Duration: semesterialDecember 2011

Contents• Intro• Project Overview • Project Goals • Requirements• Architecture• Micro Architecture• Testability & GUI• Schedule

Intro• In many projects, there is a tradeoff between

hardware and software implementation.• Hardware benefits:

o Shorter computation timeo Lower power consumptiono Reduced physical sizeo Minimum resourceso Good parallel processing capability

• Software benefits:o Simple implementationo Reduced cost

In this project we will focus on hardware implementation

Project Overview

GUI FPGA

Feedback

Result

Hardware implementation of calculator core :

• Positive integers

• Operands: ‘+’ , ’-’ , ’x’ , ’/ ’ , ‘^’ , ‘ { ‘ , ‘ } ‘

• Order of operations

• Manually acquisition Input via Matlab GUI

• Result display - LCD + debugging feedback

Project Goals

• Hardware implementation using FPGA

• Programming FPGA using VHDL

• Implementation of Interactive GUI (MATLAB)

• Experiencing full systemic perspective

Requirements• Hardware platform: Altera DE2 board - Cyclone

II FPGA

• Host communication via UART protocol

• Internal communication via Wishbone protocol

• Input - Data string to calculate

• Output 1 - The calculated result displayed on the

• Output 2 – Confirmation of the result (software)

Architecture

5x(6+2 2̂) =

Data packet structure8 bits

Address

Data Length

Data 0...

Data N-1

Header

Packet

Client address + R/WInner client address

Result

UART Protocol

start parity stop

8 bit word

RX PATH

UART RX

Message decode to wishbone

master

Message Decoder

CRCRead_value

Read_enable

Data [7..0]

Frame error

Frame _ok

length

address

UART_IN

TX PATH

UART TX

Message encoder

Wishbone to

Message encoder

Frame_finish

address

lenFrame_OK

Wishbone_data[7…0]

Write_enable

Wishbone_data[7..0]

UART_OUT

Calculator Core

Result Reg

Op Table

Result to wishbone

Calculator Algorithm

5 x ( 6 + 2 ^ 2 ) (5 x ( 6 + 2 ^ 2 ) )

(5 x ( 6 + 4 )) ( 5 x 10 )50(

Arithmetic Calculation Unit

xSelect op (3 bit)

Num1 (32 bit)

Num2 (32 bit)

ResMUX

Select op

Operation Table

Select valueBinary code

(Lsb’s)Operation

- 11111111 (

- 11111110 )

000 11111101 ^

001 11111100 x

010 11111011 /

011 11111010 +

100 11111001 -

- 11111000 EOC

LCD Core

Binary to Ascii

converter

RAM(digits in Ascii

Result from

wishbone

Result to LCD

RSR/W’E

DB0DB1DB2DB3DB4DB5DB6DB7

Enable0 :Write

1:Read

Register Select

Wishbone & wishbone intercon

Clock & Reset

Reset Block

Clk = 50 [MHz]

Reset_in

Sys_reset

Sys_clk = 100 [MHz]

ScheduleTasks Date #

Project Characterization & learning26.11.11 - 20.12.11 1Characterization presentation +

comments

Full characterization of all blocks 24.12.11 - 4.1.12 2

VHDL implementation of main blocks 5.1.12 – 4.2.12 3

Exams. Project paused 5.2.12 – 29.2.12 4

Continue VHDL implementation 1.3.12 – 20.3.12 5

Mid Presentation (optional due to Exams B) 22.3.12 6

Simulations & debug 25.3.12 – 5.4.12 7

Synthesis & building GUI 6.4.12 – 20.4.12 8

Integration and Lab testing 21.4 – 10.5.12 9

End of semester presentation 15.5.12 10

FPGA Calculator Core

Documents

FP51 (FPGA based 1T 8051 core)

A Profiler for a Multi-Core Multi-FPGA System

Chameleon FPGA core development (draft version 20130530)

Intel nehalem processor core made FPGA synthesizablecs150/sp10/Collections/Papers/nehalem... · Intel R Nehalem Processor Core Made FPGA Synthesizable Graham Schelle1, Jamison Collins1,

Implementation of Soft-core processor on FPGA (Final Presentation)

TMBox: A Configurable 16-core Hybrid TM FPGA prototype Osman Unsal

FPGA Design Using the LEON3 Fault Tolerant Processor Core

ASMI Parallel II Intel® FPGA IP Core User Guide · ASMI Parallel II Intel® FPGA IP Core User Guide The ASMI Parallel II Intel® FPGA IP core provides access to the Intel FPGA configuration

Intel® FPGA Power and Thermal Calculator User Guide · Calculator. 2.1. Availability. For Intel Agilex and Intel Stratix 10 devices, the Intel FPGA Power and Thermal Calculator (PTC)

SiFive Core IP FPGA Eval Kit User Guide v3p0...This guide will help you download and ﬂash the Core IP FPGA Eval Kit image to an FPGA development board. It will help you install software

Intel® FPGA HDMI IP Core User Guide€¦ · 3 Intel FPGA HDMI Getting Started ... A Intel FPGA HDMI IP Core User Guide Archives ... between a PC and TV, or between a device such

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256 FPGA Fault Injection IP Core User Guide Intel® FPGA Fault Injection IP Core User Guide The Intel® FPGA Fault Injection IP core injects errors into the configuration RAM (CRAM)

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Intel FPGA PHYLite for Parallel Interfaces IP Core User · PDF fileInput Buffer Reference Voltage ... Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide ... FPGA PHYLite

SPECULATIVE EXECUTION MULTI-CORE AND FPGA ...alfa.di.uminho.pt/~ammm/files/reportsoc13.pdfSPECULATIVE EXECUTION MULTI-CORE AND FPGA NELDER-MEAD IMPLEMENTATIONS FOR HIGH PERFORMANCE

Dataflow toolset for soft-core processors on FPGA for image ...Dataﬂow toolset for soft-core processors on FPGA for image processing applications Burak Bardak, Fahad Manzoor Siddiqui,

The LINPACK Benchmark on a Multi-Core Multi-FPGA System … · The LINPACK Benchmark on a Multi-Core Multi-FPGA System by ... The LINPACK Benchmark on a Multi-Core Multi ... portion