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Flip-Flops
ELCTEC-131
Flip-Flop Definition
A gated latch with a clock input.
The sequential circuit output changes when its CLOCK input detects an edge.
Edge-sensitive instead of level-sensitive.
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CLOCK Definitions Positive edge:
◦ The transition from logic ‘0’ to logic ‘1’
Negative edge:
◦ The transition from logic ‘1’ to logic ‘0’
Symbol is a triangle on the CLK (clock) input of a flip-flop.
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CLOCK Definitions
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DFF
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Positive Edge-Triggered D Flip-Flop Function Table
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CLK D Qt+1 1tQ + Function
↑ 0 0 1 RESET ↑ 1 1 0 SET 0 X Qt tQ Inhibited
1 X Qt tQ Inhibited
↓ X Qt tQ Inhibited
Positive-Edge Triggered D Flip-Flop Function Table
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Latch/Flip-Flop Behavior
The LATCH transfers data from the data inputs to Q on either a HIGH or LOW voltage level at the ENABLE input.
The FLIP-FLOP transfers data from the data inputs to Q on either the POSITIVE (rising), or NEGATIVE (falling) edge of the clock.
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Latch/Flip-Flop Behavior
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Latch/Flip-Flop Behavior
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JK Flip-Flop
Two inputs with no illegal input states.
With J and K both HIGH, the flip-flop toggles between opposite logic states with each applied clock pulse.
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JK Flip-Flop
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Negative Edge-Triggered JK Flip-Flop Function Table
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CLK J K Qt+1
Function
↓ 0 0 Qt No change ↓ 0 1 0 1 RESET ↓ 1 0 1 0 SET
↓ 1 1
Qt Toggle
0 X X Qt
Inhibited
1 X X Qt
Inhibited
↑ X X Qt
Inhibited
Negative Edge-Triggered JK Flip-Flop Function Table
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Toggle Applications
Used to divide an input frequency in half.
By cascading toggling flip-flops, a counter is created.
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Toggle Applications
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Toggle Applications
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Synchronous Versus Asynchronous Circuits
Synchronous circuits have sequential elements whose outputs change at the same time.
Asynchronous circuits have sequential elements whose outputs change at different times.
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Synchronous Versus Asynchronous Circuits
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Synchronous Versus Asynchronous Circuits
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Disadvantages of Asynchronous Circuits
Difficult to analyze operations.
Intermediate states that are not part of the desired design may be generated.
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Synchronous and Asynchronous Inputs Synchronous inputs of a flip-flop only affect the
output on the active clock edge.
Asynchronous inputs of a flip-flop change the output immediately.
Asynchronous inputs override synchronous inputs.
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Flip-Flop Asynchronous Inputs Preset:
◦ An asynchronous set function, usually designated as
Clear:
◦ An asynchronous reset function, usually designated as
Both Preset and Clear usually have LOW input active levels.
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PRE
CLR
Flip-Flop Asynchronous Inputs
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JK Flip-Flop Asynchronous Inputs Function Table
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𝑃𝑃𝑃𝑃𝑃𝑃������ 𝐶𝐶𝐶𝐶𝑃𝑃������ CLK J K Qt+1 𝑄𝑄𝑡𝑡+1������ Function
0 1 X X X 1 0 PRESET
1 0 X X X 0 1 Clear
0 0 X X X 1 1 Forbidden
1 1 Flip-Flop Operates Synchronously
JK Flip-Flop Asynchronous Timing Diagram
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Unused Preset and Clear Inputs
Disable by connecting to a logic HIGH (for active-LOW inputs).
In Quartus II the asynchronous inputs of all flip-flop primitives are set to a default level of HIGH.
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Master Reset
An asynchronous input used to set a sequential circuit to a known initial state.
Usually a RESET tied to the inputs of all flip-flops.
When activated, the output of the sequential circuit goes LOW.
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CLR
Master Reset
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Master Reset
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Experiment 20
NAND Latch
4-Bit D latch
4-Bit D Flip-Flop
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