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Micro-RDCMicroelectronics Research Development CorporationMicro-RDCMicroelectronics Research Development Corporation
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Experimental Characterization ofSEE of CMOS 90 nm PLL for the
Identification of DominantResponse Circuits
S. Ardalan, W. Burke, D. Mavis,and P. Eaton
Microelectronics Research and Development Corporation
April 13, 2010
Nineteenth Annual Single-Event Effects Symposium
Micro-RDCMicroelectronics Research Development Corporation
Micro-RDCMicroelectronics Research Development CorporationMicro-RDCMicroelectronics Research Development Corporation
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Topics
• Milli-Beam Overview and Features• PLL Block Diagram and Layout• Milli-Beam Raster Scan of PLL Design• Correlate PLL Errors to Physical Layout• PLL Modeling, Dynamics and Jitter• Measurement of Loss of Lock and
Transient Behaviour
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Milli-Beam Overview and Features• Precise beam collimation for use at the LBL cyclotron
– New hardware and software to raster scan complex ICs– Achieve spatial resolutions between 5 µm and 500 µm
• Hardware– Primary square aperture (2-orthogonal slits) stepped <1 µm precision– Secondary scattering cleanup aperture controlled from second stage– Displacement sensors provide error feedback signal for corrections
• Software– Computes coordinate transformations, sets beam position, controls run– Provides FPGA test board with positions for inclusion in error message
• Independent ICs for beam characterization and dosimetry– Homogeneous RAM for location and intensity profile measurement– Specially designed beam monitor ICs placed upstream of apertures– At preset fluences: block the beam, stop data acquisition, step apertures, update
FPGA test board with new position, resume data acquisition, unblock the beam
Dave Mavis, et. al. "New Test and Analysis Approaches for SEECharacterization,"GOMACTech-10, 24 March 2010
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Micro-RDCMicroelectronics Research Development CorporationMicro-RDCMicroelectronics Research Development Corporation
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Milli-Beam Schematic
Beam
DUT
PrimaryAperture
SecondaryAperture
Beam FluenceMonitor ICs
Rapid, Dual,Symmetric Shutter
Vacuum ChamberEntrance Port
DisplacementSensors
Dave Mavis, et. al. "New Test and Analysis Approaches for SEECharacterization,"GOMACTech-10, 24 March 2010
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Micro-RDCMicroelectronics Research Development CorporationMicro-RDCMicroelectronics Research Development Corporation
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PLL Block Diagram
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Micro-RDC PLL LayoutIBM 90nm CMOS 9LP Process
644
390
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Micro-RDC PLL Silicon Bonded Out
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Raster Scan of PLL Design• Scan a 100 µm square beam over the PLL circuitry
– Better approach than trying to test standalone circuit components– Monitor lock signal and measure recovery time– Correlate observed errors to specific circuits (CP, VCO, PSD, /N, M)
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Correlate PLL Errors to Physical Layout
Design Layout Milli-Beam Error Contours
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97 100
103
106
109
112
115
118
S1
S4
S7
S10
S13
S16
S19
S22
S25
S28
S31
S34
S37
S40
S43
S46
S49
S52
S55
S58
S61
115-120110-115105-110100-10595-10090-9585-9080-8575-8070-7565-7060-6555-6050-5545-5040-4535-4030-3525-3020-2515-2010-155-100-5
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Hanumolu, P.K.; Brownlee, M.; Mayaram, K.; Un-Ku Moon,“Analysis ofcharge pump phase-locked loops”, Circuits and Systems I: RegularPapers, IEEE Transactions on Circuits and Systems I: Fundamental Theoryand Applications, Volume 51, Issue 9, Date: Sept. 2004, Pages: 1665 – 1674
Modeling the Charge Pump for High Level Simulation
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The PLL bandwidth can be defined in terms of the loop gain
PLL Dynamics
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PLL Jitter Analysis
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The rms jitter in the synthesized clock
The VCO jitter due to VCO phase noise
Beomsup Kim; Weigandt, T.C.; Gray, P.R. ,PLL/DLL system noise analysis forlow jitter clock synthesizer design, IEEE International Symposium on Circuitsand Systems, 1994. ISCAS '94., 1994 Volume 4, Date: 30 May-2 Jun 1994,Pages: 31 - 34 vol.4
PLL Jitter
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Jitter Performance with DSET
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Jitter Performance with DSET High Bandwidth
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Lock Detection with Transparent Mode
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High Speed Daughter Card
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Scope Screen Capture of the Outputs of 90nm PLL During aLock Recovery after Switching LD0 High to Low at 50MHz.
CH1 (Yellow) Lock signal active low
CH2 (Blue) vco512
CH3 (Violet) clkout512
CH4 (Green) ref_clk_in
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Scope Screen Capture of the Outputs During aLock Condition at 50MHz
CH1 (Yellow) Lock signal activelow
CH2 (Blue) vco512
CH3 (Violet) clkout512
CH4 (Green) ref_clk_in
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