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EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
UG-564One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADAU1962A/ADAU1966A High Performance,
Low Power Multibit Sigma-Delta DAC
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 63
PACKAGE CONTENTS ADAU1962A/ADAU1966A evaluation board
(EVAL-ADAU1962AZ/EVAL-ADAU1966AZ) USBi control interface board USB cable 12 V desktop supply (Revision A PCB) or 6 V (Revision B PCB)
OTHER SUPPORTING DOCUMENTATION ADAU1962A data sheet ADAU1966A data sheet
EVALUATION BOARD OVERVIEW This user guide describes the design and setup of the evaluation board for the ADAU1962A or the ADAU1966A. ADAU196xA refers to either the ADAU1962A or the ADAU1966A. Because the ADAU1962A is a 12-channel device and the ADAU1966A is a 16-channel device, DAC Output 13 through DAC Output 16 do not function on the ADAU1962A evaluation board.
Two revisions of the evaluation board are available: the Revision A printed circuit board (PCB) and the Revision B PCB.
For the Revision A PCB, the evaluation board must be connected to an external 12 V dc power supply and ground. On-board regulators derive 5 V and 3.3 V supplies for the ADAU196xA and peripherals. For the Revision B PCB, the evaluation board must be connected to an external 5 V to 6 V dc power supply and ground (6 V maximum input to the board). On-board regulators derive 3.3 V supplies for the ADAU196xA and peripherals.
The ADAU196xA can be controlled through either an I2C or SPI interface. A small external interface board, the EVAL-ADUSB2EBZ USBi board, connects to a PC USB port and provides either I2C or SPI access to the evaluation board through a ribbon cable.
A graphical user interface (GUI) program, the Automated Register Window Builder, is provided for easy programming of the chip in a Windows® PC environment. The evaluation board allows demonstration and performance testing of most ADAU196xA features, including high performance DAC operation.
The board has an S/PDIF receiver with RCA and optical connectors, as well as a discrete serial audio interface. Analog outputs are accessible via eight stereo TRS mini jacks.
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 2 of 63
FUNCTIONAL BLOCK DIAGRAM—REVISION A PCB
S/PDIFINTERFACE
SDPINTERFACE
CONTROLINTERFACE
CLOCKAND
DATAROUTING
DAC 1TO
DAC 16
POWER SUPPLY
ADAU196xA
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1
Figure 1.
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 3 of 63
TABLE OF CONTENTS Package Contents .............................................................................. 1
Other Supporting Documentation ................................................. 1
Evaluation Board Overview ............................................................. 1
Functional Block Diagram—Revision A PCB ............................... 2
Revision History ................................................................................ 3
Setting Up the Evaluation Board—Revision A PCB ..................... 5
Standalone Mode ........................................................................... 5
I2C and SPI Control ...................................................................... 5
Automated Register Window Builder Software Installation ...... 6
Hardware Setup—USBi ................................................................ 6
Powering the Board ...................................................................... 7
Resetting the Evaluation Board ................................................... 7
Setting Up the Master Clock (MCLK) ....................................... 8
Selecting PLL ................................................................................. 8
Routing Digital Audio Connections ........................................... 9
Connecting Analog Audio Cables ............................................. 10
Modification for Differential Output ....................................... 10
Modification to Use the N Output ............................................ 10
Schematics and Artwork—Revision A PCB ................................. 11
Bill of Materials—Revision A PCB ................................................ 27
Functional Block Diagram—Revision B PCB ............................. 31
Setting Up the Evaluation Board—Revision B PCB ................... 32
Standalone Mode ........................................................................ 32
I2C and SPI Control .................................................................... 32
SigmaStudio Software Installation ............................................ 33
Automated Register Window Builder Software Installation ... 33
Hardware Setup—USBi .............................................................. 34
Powering the Board .................................................................... 34
Resetting the Evaluation Board ................................................. 35
Setting Up the Master Clock (MCLK) ..................................... 35
Selecting the PLL loop filter ...................................................... 36
Routing Digital Audio Connections ......................................... 36
L/R and Bit Clock routing .......................................................... 38
Level Translators ......................................................................... 39
Connecting Analog Audio Cables ............................................. 39
Modification for Differential Output ....................................... 39
Modification to Use the N Output............................................ 39
Schematics and Artwork—Revision B PCB ................................ 40
Bill of Materials—Revision B PCB ................................................ 57
REVISION HISTORY 7/15—Rev. A to Rev. B Added Revision B PCB ...................................................... Universal Changes to Package Contents Section and Evaluation Board Overview Section .............................................................................. 1 Changed Functional Block Diagram Section to Functional Block Diagram—Revision A PCB Section ..................................... 1 Changed Setting Up the Evaluation Board Section to Setting Up the Evaluation Board—Revision A PCB Section .......................... 3 Changed Schematics and Artwork section to Schematics and Artwork—Revision A PCB Section ................................................. 9 Changed Bill of Materials Section to Bill of Materials—Revision A PCB Section ..................................................................................... 25 Added Functional Block Diagram—Revision B PCB Section and Figure 36 ................................................................................... 30 Added Setting Up the Evaluation Board—Revision B PCB Section and Figure 37 to Figure 57 ............................................... 31 Added Schematics and Artwork—Revision B PCB Section and Figure 58 to Figure 74 ..................................................................... 39 Added Bill of Materials—Revision B PCB Section and Table 4 ... 56 7/13—Revision 0: Initial Version
AD9913/PCBZ
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 4 of 63
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 5 of 63
SETTING UP THE EVALUATION BOARD—REVISION A PCB STANDALONE MODE The ADAU196xA has a standalone mode, which allows the user to choose between a limited number of operation modes without the need for a control interface. Applying a jumper across JP21, as shown in Figure 2, pulls SA_MODE (Pin 46) high enabling standalone mode in the ADAU196xA. The SA_MODE selections are listed in Table 1.
Table 1. Standalone Modes Pin Setting Description Pin 42 0 Master serial audio interface 1 Slave serial audio interface Pin 43 0 256 × fS 1 384 × fS Pin 44 0 Reserved, set to 0 Pin 45 0 I2S mode 1 TDM mode Pin 32 to Pin 31 00 TDM4, pulse 01 TDM8, pulse 10 TDM16, pulse 11 TDM8, 50% duty
On the EVAL-ADAU196xAZ, each of the four control port pins of the ADAU196xA are brought out to a block of jumpers, allowing the user to assign each pin to either the I2C or SPI ports. In standalone mode, these jumpers can connect the individual pins to high (IOVDD) or low (GND) to put the ADAU196xA in the desired mode.
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Figure 2. SA_MODE—Slave, 256 × fS, I2S
The EVAL-ADAU196xAZ arrives configured for S/PDIF input. The S/PDIF receiver operates as a clock master, putting out an I2S stream at 256 × fS. For quick startup, the ADAU196xA is in standalone mode with the settings shown in Figure 2.
Pin 42 is pulled high (1) and Pin 43 to Pin 45 are pulled low (0). According to Table 1, this puts the ADAU196xA in slave mode, running at 256 × fS, and the audio serial port in I2S mode. In Figure 2, notice that the jumper for Pin 42 is beneath the label for 1 and the other pins are assigned to 0.
PIN 31
PIN 32
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Figure 3. SA_MODE—Master, 384 × fS, TDM
Figure 3 shows the other options for each SA_MODE config-uration pin; master mode, running at 384 × fS, and the audio serial port in TDM mode. When the ADAU196xA is in TDM mode, Pin 31 and Pin 32 can be pulled high (IOVDD) or low (GND) to achieve the modes listed in Table 1. The correct pins are located in the top left corner of Figure 3.
I2C AND SPI CONTROL The evaluation board can be configured for live control over the registers in the ADAU196xA. When the Automated Register Window Builder software is installed and the USBi control interface is plugged into the board, the software can control the ADAU196xA. For this configuration, the ADAU196xA must be assigned to I2C mode using Address 00. See Figure 4 for the correct jumper positions.
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 6 of 63
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Figure 4. ADAU196xA I2C Control, Address 00
The Automated Register Window Builder controls the ADAU196xA and is available for download at www.analog.com/ADAU1962A or www.analog.com/ADAU1966A.
The ADAU196xA can also be put in SPI mode for control by other means. See Figure 5 for the correct jumper positions.
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Figure 5. ADAU196xA SPI Control
AUTOMATED REGISTER WINDOW BUILDER SOFTWARE INSTALLATION The Automated Register Window Builder is a program that launches a graphical interface for direct, live control of the ADAU196xA registers. The GUI content for a specific device is defined in a device-specific .xml file; these files are included in the software installation.
To install the Automated Register Window Builder software, follow these steps:
1. Go to www.analog.com/ADAU1962A or www.analog.com/ADAU1966A and download the ARWBvXX.zip file from the product page.
2. Open the downloaded ARWBvXX.zip file and extract the files to an empty folder on your PC.
3. Install the Automated Register Window Builder by double-clicking setup.exe and following the prompts. A computer restart is not required.
4. Copy the .xml file for the ADAU196xA from the extraction folder into the folder C:\ProgramFiles\Analog Devices Inc\ AutomatedRegWin, if it is not already installed.
HARDWARE SETUP—USBi To set up the USBi hardware, follow these steps:
1. Plug the USBi ribbon cable into the J12 I2C/SPI port. 2. Connect the USB cable to your computer and to the USBi. 3. When prompted for drivers,
a. Choose Install from a list or a specific location. b. Choose Search for the best driver in these locations. c. Check the box for Include this location in the search. d. Find the USBi driver C:\Program Files\Analog
Devices Inc\AutomatedRegWin\USB drivers. e. Click Next. f. If prompted to choose a driver, select CyUSB.sys. g. If the PC is running Windows® XP and a message
appears stating that the software has not passed Windows logo testing, click Continue Anyway.
The user can now open the Automated Register Window Builder application and load the .xml file for the device on the evaluation board. Plug the 10-way ribbon cable on the USBi into the I2C/SPI port (J12) on the evaluation board.
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 7 of 63
POWERING THE BOARD The EVAL-ADAU196xAZ evaluation board requires a power supply input of +12 V dc and ground to the power jack; +12 V draws ~150 mA at higher sample rates with all channels running.
The on-board regulators provide 5 V and 3.3 V rails. The 5 V rail is derived from +12 V by a switching regulator; it supplies 5 V for the 3.3 V power supply and other peripherals via the SDP interface optional resistors R133 and R156. The 3.3 V rail is derived from the 5 V supply by an LDO linear regulator; it provides voltage to AVDD and IOVDD as well as other active peripherals.
AVDD and IOVDD are connected on the board using 0R00 Ω 0805 package resistors. If the user needs to insert a different power source, or measure current draw of the entire board, it can be accomplished using these 0 Ω jumpers.
REGULATOROUTPUT
REGULATOR SIDE
LOAD SIDE
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Figure 6. AVDD and IOVDD Jumper Resistors
The ADAU196xA has an internal voltage regulator that allows the user to derive DVDD and PLLVDD from the AVDD voltage source. The external PNP transistor Q1 and the passives, C36, C40, and R56, make the regulator circuit shown in Figure 7. Both JP9 and JP11 must be shorted to activate the circuit; JP9 supplies the emitter of the PNP and JP11 powers VSUPPLY (Pin 25) on the ADAU196xA.
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Figure 7. ADAU196xA Internal Regulator Jumpers
Links are provided along each ADAU196xA power rail to provide access for current measurement of only the ADAU196xA (see Figure 8). These links also allow the user to directly supply voltage from an outside source. The square pins and the test points are the load side. All four links must be connected for proper operation.
115
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Figure 8. ADAU196xA Power Links
RESETTING THE EVALUATION BOARD The EVAL-ADAU196xAZ has provisions for resetting and powering down the ADAU196xA. S2 on the evaluation board, shown in Figure 9, is a momentary reset switch that pulls the master reset (MR) line low; this line controls the reset generator U10. MR is also connected to the USBi and the SDP interface connectors through steering diodes and protection resistors so that outside devices can control the reset state of the evaluation board as shown in Figure 25. The power-down jumper JP5 allows the MR line to be tied low. The output of the reset generator drives the PU/RST line.
The PU/RST line is directly connected to two devices: the S/PDIF receiver and the ADAU196xA. The line is held low by a pull-down resistor until the reset generator U10 asserts the line high as shown in Figure 25. The PU/RST line is also connected to a pin on the SDP interface through a steering diode and protection resistor allowing external reset control.
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Figure 9. Reset Switch and Power-Down Jumper
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 8 of 63
SETTING UP THE MASTER CLOCK (MCLK) The MCLK routing on the evaluation board is handled by a block of jumpers, J5, allowing any one of four sources to be selected—S/PDIF, the SMA connector, active OSC, and the INTF connector. The board arrives with S/PDIF selected as shown in Figure 10.
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Figure 10. SPDIF Selected as MCLK Source
The evaluation board has a 12.288 MHz active oscillator that can be selected by shorting the OSC_EN jumper JP8 and selecting OSC on J5 as shown in Figure 11.
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Figure 11. Active OSC Enabled and Selected as MCLK
The evaluation board can be set to receive MCLK from the SDP interface connectors. To do so, select the INTF setting on J5 and enable the MCLK buffer by shorting jumper J6, MCLK_SEL, as shown in Figure 12.
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Figure 12. INTF Input Enabled and Selected
SELECTING PLL The PLL in the ADAU196xA is very flexible, allowing the device to run from a wide range of either MCLK or LRCLK frequencies.
It is also possible to shut the PLL off altogether and use the device in direct lock mode; functionality with no PLL is limited to 256 × fS.
115
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3
Figure 13. MCLK Selection for PLL Loop Filter
By default, the ADAU196xA runs from the PLL using MCLK as the clock source. The MCLK loop filter must be selected using JP2 as shown in Figure 13.
115
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4
Figure 14. LRCLK Selection for PLL Loop Filter
DLRCLK can be selected as the PLL clock source using the PLL and Clock Control 0 Register [7:6]. In this case, the LRCLK loop filter must be selected as shown in Figure 14. If DLRCLK is selected as the PLL clock, there is no need for an MCLK.
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 9 of 63
ROUTING DIGITAL AUDIO CONNECTIONS The ADAU196xA evaluation board has two separate inputs for digital audio signals: the S/PDIF and the SDP interface.
The S/PDIF receiver can handle either of two options: S/PDIF uses the RCA jack, J1, and optical uses the Toslink jack, U1. The input is selected using S1 as shown in Figure 15.
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Figure 15. S/PDIF Input Selector Switch SW1
A series of resistors have been provided to set the functional mode of the S/PDIF receiver as shown in Figure 16. By default, the S/PDIF receiver runs in master mode, 256 × fS, I2S format. Consult the data sheet for the S/PDIF receiver to make the required changes to the hardware mode.
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6
Figure 16. S/PDIF Mode Selection Resistors
The jumpers shown in Figure 17 are set for the S/PDIF receiver to drive the DBCLK and DLRCLK clock ports and the eight DSDATAx lines of the ADAU1962A/ADAU1966A. JP22 selects the input to a buffer; the output of this buffer shows up on the right-hand column of JP13 to JP20.
The pins in the middle column of these jumpers are connected to the DSDATAx pins of the ADAU196xA through the appro-priate line termination. DBCLK and DLRCLK selections are made with JP10 and JP12 where the middle pins are connected to the DBCLK and DLRCLK pins of the ADAU196xA.
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Figure 17. S/PDIF Data and Clock Routing
The system development platform (SDP) interfaces, J6 and J8, make up a standard interconnect within Analog Devices, Inc. They provide for the transfer of digital audio clocks and control between boards. See the pinout included in the schematic in Figure 27.
Figure 18 shows the jumper configuration for using the SDP interface connector as the digital audio source. JP22 is set so that the DSDATA1 source from the SDP interface is driving the buffer, and this buffer is connected to all eight DSDATA inputs of the ADAU196xA. JP10 and JP12 are set for the ADAU196xA to run in slave mode from clocks supplied by the SDP interface.
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Figure 18. SDP Interface DSDATA1 Distribution
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 10 of 63
CONNECTING ANALOG AUDIO CABLES There are two forms of the analog outputs of the ADAU196xA evaluation board: differential and single ended.
The board comes standard with the single-ended outputs appearing on through-hole test points as well as on the TRS mini connectors.
The single-ended outputs of the ADAU196xA drive the connectors directly, through a simple 1-pole RC filter with appropriate ac coupling.
To evaluate the differential outputs, one can modify the board to accomplish this with a little soldering and a few parts.
MODIFICATION FOR DIFFERENTIAL OUTPUT The ADAU196xA evaluation board can be modified to be used differentially.
See Figure 19 for the schematic of the standard filter. To modify for balanced operation, perform the following steps for each channel:
1. Remove R6 (0 Ω jumper). 2. Change R1 from 470 Ω to 237 Ω (0402). 3. Add R2 (237 Ω, 0402). 4. Add C3 (10 μf). 5. Add R4 (49.9 kΩ, 0402).
++
R1470Ω
R2OPEN R3
49.9kΩR4OPEN
R5OPEN
R60Ω
C12.7nF
C2
C3 OPEN
DACP
DACN
OUTP
OUTN
10µF
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Figure 19. Typical Evaluation Board Filter
MODIFICATION TO USE THE N OUTPUT The ADAU196xA evaluation board can be modified to use the DACN output instead of the DACP output. If the user needs to invert all the channels, it is recommended to do so in the software using the DAC CONTROL 2 Register or by inverting the I2S data stream.
See Figure 19 for the schematic of the standard filter. To modify to use the N output, perform the following steps for each channel:
1. Move R6 over to R5 (0 Ω jumper). 2. Move R1 over to R2 (470 Ω). 3. Move C2 over to C3 (10 μF). 4. Move R3 over to R4 (49.9 kΩ). 5. Install a jumper between the N and P output test points.
Note that if new parts are to be used for R2, R4, R5, and C3, then R1, R3, R6, and C2 must be removed.
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 11 of 63
SCHEMATICS AND ARTWORK—REVISION A PCB
ADAU196xA
DAC DIFF OUTPUT 1 TO 8 PASSIVE RC 1 POLE
DAC DIFF OUTPUT 9 TO 16 PASSIVE RC 1 POLE
POWER SUPPLY REGULATORS
5V = SWITCHING SUPPLY
3.3V = LINEAR SUPPLY DERIVED FROM 5V
INT REGXISTOR
PLLVDDDVDD
AVDD = 3.3V
IOVDD = 3.3V
0Ω JUMPERS FOR EACH SUPPLYFOR CURRENT MEASUREMENT
USBi CONTROL PORT,PD JUMPERS,
SA_MODE JUMPERS,COM PORT JUMPERS,
RESET SWITCH
S/PDIF RECEIVER
DSP/FPGA INTERFACE
BCLK, LRCLK,SDATA JUMPERS
WITH BUFFER
12V DCINPUT
OPTICAL AND COAX INPUTS,HARDWARE MODECONTROL JUMPERS
ALLOWS FORDIRECT
CONNECT TO DUT
SINGLE-ENDED OUTPUTS ON TRS MINI JACKS
3.3V FOR S/PDIF COREIOVDD COMES FROM DUT IOVDD
DESKTOP SUPPLY24V DC INPUT MAX!
CM OUTPUT ON TP
BUFFERED MCLKO
CLKs
CLKs AND DATA
3.3V/2.5V
SINGLE-ENDED OUTPUTS ON TRS MINI JACKS
MCLK SOURCES S/PDIF ACTIVE OSC CRYSTAL DSP INTF EXT IN
11
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Figure 20. Schematic, Page 1—EVAL-ADAU196xAZ Block Diagram
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 12 of 63
11588-021
Enab
le
ADAU
1966
Volta
geRe
gula
tor
MCL
KLR
CLK
Seepages5&6forjumpers
Stan
dalo
ne
Mod
esM
aste
rSA
ISla
veSA
I25
6xfs
,PL
L38
4xfs
,PL
LN
oFu
nction
,ca
nbe
set
to0
or1
No
Func
tion
I2S
TDM
TDM
4,Pu
lse
TDM
8,Pu
lse
TDM
16,
Puls
eTD
M8,
50%
Dut
yCy
cle
0 1 0 1 0 1 0 1 00 01 10 11
Pin
42
Pin
43
Pin
44
Pin
45
Pins
32:3
1
C76
0.47
uF
C37
C68
0.10
uFC6
50.
10uF
C77
C43
0.47
uF
C72
0.47
uFC4
50.
47uF
C75
C41C71
C67
C42
C47
C44
C53
JP1
JP3
+C1
3410
uF+
C130
10uF
TP66
TP63
TP26
TP21
TP25
TP44
B
C
E
C
Q1
ZX5T
953G
TA
C36
C40
+C1
2610
uF
R56
1k50
TP50
TP53
C18
2.2n
FN
P0C2
139
nFR25
3k32
AB
J P2
C17
390p
FC2
05.
6nF
R27
562R
1 3 5 7 9
2 4 6 8 1011 13 15 17 19
12 14 16 18 20 2221
2423
2625 27
28
J11
HEA
DER
_28W
AY_U
NSH
ROUD
+C1
2510
uF+
C127
10uF
+C1
2910
uF
JP11
+C1
2810
uF
+C1
3110
uF
+C1
3310
uF
27D
BCLK
28D
LRCL
K
31D
SDAT
A8
32D
SDAT
A7
33D
SDAT
A6
34D
SDAT
A5
35D
SDAT
A4
36D
SDAT
A3
37D
SDAT
A2
38D
SDAT
A1
30DGND
21DGND
19M
CLKO
18XT
ALO
17M
CLKI
/XTA
LI
16PL
LVD
D
15LF
14PL
LGN
D
47PU
/RST
46SA
_MO
DE
45CL
ATCH
/AD
DR0
44CC
LK/S
CL
43CO
UT/
SDA
42CD
ATA/
ADD
R1
50D
AC1P
51D
AC1N
52D
AC2P
53D
AC2N
54D
AC3P
55D
AC3N
56D
AC4P
57D
AC4N
59D
AC_B
IAS1
60D
AC_B
IAS2
64D
AC5P
65D
AC5N
66D
AC6P
67D
AC6N
68D
AC7P
69D
AC7N
70D
AC8P
71D
AC8N
72D
AC9P
73D
AC9N
74D
AC10
P75
DAC
10N
76D
AC11
P77
DAC
11N
78D
AC12
P79
DAC
12N
1D
AC_B
IAS3
2D
AC_B
IAS4
4D
AC13
P5
DAC
13N
63TS
_REF
62CM
40DGND
24 VDRIVE
23 VSENSE
25 VSUPPLY
39 IOVDD
41 DVDD
22 IOVDD
29 DVDD
12 AVDD4
3 AVDD3
58 AVDD2
49 AVDD1
20 DVDD
6D
AC14
P7
DAC
14N
8D
AC15
P9
DAC
15N
10D
AC16
P11
DAC
16N
13AGND4
80AGND3
61AGND2
48AGND1
26DGND
U6
ADAU
1966
AWBS
TZ
JP21
R138
10k0
TP57
JP9
JP7
JP4
TP27
TP45
TP71
JP23
[2] 1
966_
CDAT
A/AD
DR1
[2] 1
966_
COUT/
SDA
[2] 1
966_
CCLK
/SCL
[2]19
66_C
LATC
H/A
DD
R0
[6,9
]PU
_RST
[3]
DAC
1P[3
]D
AC1N
[3]
DAC
2P[3
]D
AC2N
[3]
DAC
3P[3
]D
AC3N
[3]
DAC
4P[3
]D
AC4N
TS_R
EF
[3]
DAC
5P[3
]D
AC5N
[3]
DAC
6P[3
]D
AC6N
[3]
DAC
7P[3
]D
AC7N
[3]
DAC
8P[3
]D
AC8N
[4]
DAC
9P[4
]D
AC9N
[4]
DAC
10P
[4]
DAC
10N
[4]
DAC
11P
[4]
DAC
11N
[4]
DAC
12P
[4]
DAC
12N
[4]
DAC
13P
[4]
DAC
13N
[4]
DAC
14P
[4]
DAC
14N
[4]
DAC
15P
[4]
DAC
15N
[4]
DAC
16P
[4]
DAC
16N
LF
[6]
MCL
KI/X
TALI
[2] VDRIVE
[2] VSENSE
[2] VSUPPLY
AVD
D
IOVD
D
[2]
VSEN
SE
[2]
VSUP
PLY
[2]
VDRI
VE
[2]
VSEN
SE
[2]
VSEN
SE
1966
_IO
VDD
1966
_DVD
D
AVD
D
PLLV
DD
PLLV
DD
GN
D
[6]
XTAL
O
[6]
MCL
KO
IOVD
D[5]
1966
_DSD
ATA1
[5]
1966
_DSD
ATA2
[5]
1966
_DSD
ATA3
[5]
1966
_DSD
ATA4
[5]
1966
_DSD
ATA8
[5]
1966
_DSD
ATA7
[5]
1966
_DSD
ATA6
[5]
1966
_DSD
ATA5
[5]
1966
_DLR
CLK
[5]
1966
_DBC
LK
SA_M
OD
E
[2]
1966
_CLA
TCH
/AD
DR0[2]
1966
_CO
UT/
SDA
[2]
1966
_CCL
K/SC
L
[6,7
]US
BI_C
LATC
H_A
[6,7
]USB
I_CC
LK[6
,7]
USB
I_SC
L
[2]
CM
[2]
1966
_AVD
D 1966
_AVD
D
[2]
1966
_CD
ATA/
ADD
R1
[6,7
]US
BI_C
OUT
[ 6,7
]US
BI_S
DA
[6,7
]US
BI_C
DAT
A
IOVD
D
[2]
CM
Figure 21. Schematic, Page 2—ADAU196xA, PLL Loop Filter (LF) Selection and Internal Regulator
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 13 of 63
R9
2
OP
EN
R9
1
47
5R
TP
79
TP
78
C8
4
2.7
nF
R9
4
OP
EN
R9
3
47
5R
TP
81
TP
80
C8
5
2.7
nF
R9
8
OP
EN
R9
7
47
5R
TP
85
TP
84
C8
7
2.7
nF
R9
6
OP
EN
R9
5
47
5R
TP
83
TP
82
C8
6
2.7
nF
+
C9
1
10
uF
+
C9
0
OP
EN
+
C8
9
10
uF
+
C8
8
OP
EN
R1
02
49
k9
R1
01
OP
EN
R1
00
49
k9
R9
9
OP
EN
+
C9
5
10
uF
+
C9
4
OP
EN
+
C9
3
10
uF
+
C9
2
OP
EN
R1
06
49
k9
R1
05
OP
EN
R1
04
49
k9
R1
03
OP
EN
TP
10
1T
P1
00
TP
99
TP
98
TP
97
TP
93
TP
91
TP
90
R6
8
OP
EN
R7
0
47
5R
TP
61
TP
62
C6
1
2.7
nF
R7
4
OP
EN
R7
6
47
5R
TP
64
TP
67
C7
3
2.7
nF
R8
0
OP
EN
R8
2
47
5R
TP
69
TP
72
C7
9
2.7
nF
R8
6
OP
EN
R8
8
47
5R
TP
74
TP
76
C8
2
2.7
nF
+
C8
3
10
uF
+
C8
1
OP
EN
R8
9
49
k9
R8
7
OP
EN
+
C8
0
10
uF
+
C7
8
OP
EN
R8
3
49
k9
R8
1
OP
EN
+
C7
4
10
uF
+
C6
9
OP
EN
R7
7
49
k9
R7
5
OP
EN
+
C6
2
10
uF
+
C5
9
OP
EN
R7
1
49
k9
R6
9
OP
EN
TP
89
TP
87
TP
77
TP
75
TP
73
TP
70
TP
68
TP
65
R1
62
OP
EN
R1
63
OP
EN
R1
64
OP
EN
R1
65
OP
EN
R1
66
OP
EN
R1
67
OP
EN
R1
68
OP
EN
R1
69
OP
EN
R170
0R00
R171
0R00
R172
0R00
R173
0R00
R174
0R00
R175
0R00
R176
0R00
R177
0R00
RIN
G
SL
EE
VE
TIP
J3
RIN
G
SL
EE
VE
TIP
J9
RIN
G
SL
EE
VE
TIP
J10
RIN
G
SL
EE
VE
TIP
J14
[2]
DA
C1
N[2]
DA
C1
P
[2]
DA
C2
N
[2]
DA
C2
P [2]
DA
C4
N
[2]
DA
C4
P[2]
DA
C3
N
[2]
DA
C3
P
OU
T4
N
[3]
OU
T4
P
OU
T3
N
[3]
OU
T3
P
OU
T2
N
[3]
OU
T2
P
OU
T1
N
[3]
OU
T1
P
[2]
DA
C8
N
[2]
DA
C8
P[2]
DA
C7
N
[2]
DA
C7
P[2]
DA
C6
N
[2]
DA
C6
P[2]
DA
C5
N
[2]
DA
C5
P
[3]
OU
T5
P
OU
T5
N
[3]
OU
T6
P
OU
T6
N
[3]
OU
T7
P
OU
T7
N
OU
T8
N
[3]
OU
T8
P
[3]
OU
T8
P
[3]
OU
T7
P
[3]
OU
T6
P
[3]
OU
T5
P
[3]
OU
T4
P
[3]
OU
T3
P
[3]
OU
T2
P
[3]
OU
T1
P
11588-022
Figure 22. Schematic, Page 3—ADAU196xA DAC Output 1 to Output 8
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 14 of 63
R3
0
OP
EN
R3
1
47
5R
TP
28
TP
29
C2
32
.7n
F
R3
2
OP
EN
R3
3
47
5R
TP
30
TP
31
C2
42
.7n
F
R3
4
OP
EN
R3
5
47
5R
TP
32
TP
33
C2
52
.7n
F
R3
6
OP
EN
R3
7
47
5R
TP
34
TP
35
C2
62
.7n
F
R5
4
OP
EN
R5
7
47
5R
TP
51
TP
54
C4
82
.7n
F
R6
0
OP
EN
R6
4
47
5R
TP
58
TP
59
C5
42
.7n
F+
C5
5
10
uF
+C
51
OP
EN
R6
5
49
k9
R6
1
OP
EN
+
C4
9
10
uF
+C
46
OP
EN
R5
8
49
k9
R5
5
OP
EN
+
C2
2
10
uF
+
C1
9
OP
EN
R2
9
49
k9
R2
8
OP
EN
+
C1
6
10
uF
+
C1
5
OP
EN
R2
6
49
k9
R2
3
OP
EN
+
C1
4
10
uF
+
C1
3
OP
EN
R2
2
49
k9
R1
9
OP
EN
+
C9
10
uF
+
C8
OP
EN
R8
49
k9
R7
OP
EN
TP
55
TP
52
TP
49
TP
47
TP
22
TP
19
TP
18
TP
16
TP
12
TP
11
TP
10
TP
7
RIN
G
SL
EE
VE
51J
PIT R
ING
SL
EE
VE
61J
PIT R
ING
SL
EE
VE
71J
PIT R
ING
SL
EE
VE
TIP
J1
8R
40
OP
EN
R4
4
47
5R
TP
39
TP
41
C3
12
.7n
F
R4
7
OP
EN
R5
1
47
5R
TP
46
TP
48
C3
82
.7n
F+
C3
9
10
uF
+
C3
5
OP
EN
R5
2
49
k9
R4
8
OP
EN
+
C3
2
10
uF
+
C3
0
OP
EN
R4
5
49
k9
R4
1
OP
EN
TP
42
TP
40
TP
37
TP
24
R107
0R00
R1
08
OP
EN
R1
09
OP
EN
R1
10
OP
EN
R1
12
OP
EN
R1
13
OP
EN
R1
14
OP
EN
R1
15
OP
EN
R1
16
OP
EN
R117
0R00
R118
0R00
R119
0R00
R158
0R00
R159
0R00
R160
0R00
R161
0R00
[2]
DA
C1
6N
[2]
DA
C1
6P[2
]D
AC
15
N
[2]
DA
C1
5P[2
]D
AC
14
N
[2]
DA
C1
4P[2
]D
AC
13
N
[2]
DA
C1
3P
[2]
DA
C1
0N
[2]
DA
C1
0P[2
]D
AC
9N
[2]
DA
C9
P
OU
T1
0N
[4]
OU
T1
0P
OU
T9
N
[4]
OU
T9
P
[4]
OU
T1
3P
OU
T1
3N
OU
T1
4N
[4]
OU
T1
4P
[4]
OU
T1
5P
OU
T1
5N
OU
T1
6N
[4]
OU
T1
6P
[4]
OU
T1
6P
[4]
OU
T1
5P
[4]
OU
T1
4P
[4]
OU
T1
3P
[4]
OU
T1
2P
[4]
OU
T1
1P
[4]
OU
T1
0P
[4]
OU
T9
P
[2]
DA
C1
2N
[2]
DA
C1
2P[2
]D
AC
11
N
[2]
DA
C1
1P
[4]
OU
T1
1P
OU
T1
1N
[4]
OU
T1
2P
OU
T1
2N
11588-023
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 15 of 63
Figure 23. Schematic, Page 4—ADAU196xA DAC Output 9 to Output 12
B A
JP13
B A
JP14
B A
JP15
B A
JP16
B A
JP17
B A
JP18
B A
JP19
B A
JP20
2A
1O
E
4Y
U1
8
SN
74
LV
C1
G1
25
DR
LR
AB
JP2
2 C7
C7
0
4.7
pF
C6
6
4.7
pF
C6
4
4.7
pF
C6
3
4.7
pF
C6
0
4.7
pF
C5
8
4.7
pF
C5
7
4.7
pF
C5
6
4.7
pF
C5
2
2.2
pF
C5
0
2.2
pF
R6
2
33
R2
R5
9
33
R2
R6
3
33
R2
R9
0
68
R1
R8
5
68
R1
R8
4
68
R1
R7
9
68
R1
R7
8
68
R1
R7
3
68
R1
R7
2
68
R1
R6
7
68
R1
R6
6
33
R2
C1
41
2.2
pF
R1
41
33
R2
B A
JP12
B A
JP10
[9]
84
16
_S
DA
TA
[7]
INT
F_
DS
DA
TA
1
[7]
INT
F_
DB
CL
K
[7] IN
TF
_D
LR
CL
K
[7]
INT
F_
DS
DA
TA
8
[7]
INT
F_
DS
DA
TA
7
[7]
INT
F_
DS
DA
TA
6
[7]
INT
F_
DS
DA
TA
5
[7]
INT
F_
DS
DA
TA
4
[7]
INT
F_
DS
DA
TA
3
[7]
INT
F_
DS
DA
TA
2
[9]
84
16
_B
CL
K
[9]
84
16
_L
RC
LK
IOV
DD
DB
CL
K
DL
RC
LK
DS
DA
TA
8
DS
DA
TA
7
DS
DA
TA
6
DS
DA
TA
5
DS
DA
TA
4
DS
DA
TA
3
DS
DA
TA
2
DS
DA
TA
1
[2]
19
66
_D
BC
LK
[2]
19
66
_D
LR
CL
K
[2]
19
66
_D
SD
AT
A8
[2]
19
66
_D
SD
AT
A7
[2]
19
66
_D
SD
AT
A6
[2]
19
66
_D
SD
AT
A5
[2]
19
66
_D
SD
AT
A4
[2]
19
66
_D
SD
AT
A3
[2]
19
66
_D
SD
AT
A2
[2]
19
66
_D
SD
AT
A1 11588-024
Figure 24. Schematic, Page 5—BCLK, LRCLK, and SDATA Jumpers and Routing
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 16 of 63
MC
LK
so
urc
esC
LK
OU
T F
eed
US
Bi o
r A
ard
vark
US
Bi I
nte
rfac
e
MR
lin
e co
mes
fro
m U
SB
i B
oar
d R
eset
Res
et
MC
LK
So
urc
e
Po
we
r d
ow
n
12
34
56
78
J5
TP
38
1O
E
2G
ND
3
OU
TP
UT
4V
DD
U5
OS
C_
CP
PF
XC
7-1
2.2
88
MH
Z_
7M
MX
5M
M_
SM
D
R4
2
49
R9
L7
C3
3Y
1
12
.28
8M
Hz
R4
9
15
0R
C2
92
2p
F
C3
42
2p
F
R5
3
49
R9
2A
1O
E
4Y
U4
SN
74
LV
C1
G1
25
DR
LR
J2
R2
4
49
R9
C1
11
TP
20
1 3 5 7 9
2 4 6 8 10
J1
2
HE
AD
ER
_1
0W
AY
_P
OL
R1
11
3k
01
R1
55
3k
01
4V
CC
3M
R
1G
ND
2R
ES
ET
U1
0
AD
M8
11
R
C2
7
12
34
S2
R1
26
10
0k
R1
57
10
k0
JP8
R4
6
10
k0
R1
32
49
R9
C1
24
10
pF
R3
9
0R
00
J4
R3
84
9R
9
C2
81
0p
F
R1
29
49
R9
R4
3
0R
00
JP5
R5
01
M0
0
D1
0
MB
R0
53
0T
1G
[2]
MC
LK
I/XT
AL
I
IOV
DD
[2]
XT
AL
O[2
]M
CL
KO
IOV
DD
[9]
84
16
_M
CL
KI
[6,8
]M
R[2
,7]
US
BI_
SC
L[2
,7]
US
BI_
SD
A
[2,7
]U
SB
I_C
CL
K[2
,7]
US
BI_
CL
AT
CH
_A
[2,7
]U
SB
I_C
DA
TA
IOV
DD
[2,9
]P
U_
RS
T
[6,8
]
MR
IOV
DD
[7]
EI3
_M
CL
KI
[9]
OM
CK
_F
EE
D
[2,7
]U
SB
I_C
OU
T
[7]
US
BI_
5V
00
[7]
EI3
_M
CL
KO
11588-025
Figure 25. Schematic, Page 6—MCLK Selection, USBi Interface, CLKOUT Feed, and Reset Generator
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 17 of 63
1V
CC
A2
DIR
3A
14
A2
5A
36
A4
7A
58
A6
9A
71
0A
81
1G
ND
12
GN
D1
3G
ND
14
B8
15
B7
16
B6
17
B5
18
B4
19
B3
20
B2
21
B1
22
OE
23
VC
CB
24
VC
CB
U1
3
SN
74
LV
CH
8T
24
5D
BR
_8
BIT
LV
LS
HF
T
R1
43
49
R9
R1
42
49
R9
R1
37
10
k0
R1
34
10
k0
2S
CL
A3
SD
AA
7S
CL
B6
SD
AB
1V
CC
A8
VC
CB
4G
ND
5E
NU
15
PC
A9
51
7D
P-T
_I2
CB
US
RP
T_
LV
LT
RA
NS
_T
SS
OP
8
R1
44
10
k0
1V
CC
A2
DIR
3A
14
A2
5A
36
A4
7A
58
A6
9A
71
0A
81
1G
ND
12
GN
D1
3G
ND
14
B8
15
B7
16
B6
17
B5
18
B4
19
B3
20
B2
21
B1
22
OE
23
VC
CB
24
VC
CB
U1
6
SN
74
LV
CH
8T
24
5D
BR
_8
BIT
LV
LS
HF
T
R1
39
10
k0
2A
1
3A
2
7B
1
6B
2
1VCCA
8VCCB 4
GND
5D
IRU
11
SN
74
LV
C2
T4
5D
CT
R_
2B
ITL
VL
SH
FT
R1
27
10
k0
R1
46
1k
50
R1
45
3k
32
1V
CC
A2
DIR
3A
14
A2
5A
36
A4
7A
58
A6
9A
71
0A
81
1G
ND
12
GN
D1
3G
ND
14
B8
15
B7
16
B6
17
B5
18
B4
19
B3
20
B2
21
B1
22
OE
23
VC
CB
24
VC
CB
U1
7
SN
74
LV
CH
8T
24
5D
BR
_8
BIT
LV
LS
HF
T
R1
49
10
k0
R1
40
10
k0
1 2 3 4 5 6 7 891
01
11
21
31
41
51
6
R1
36
33
R0
1 2 3 4 5 6 7 891
01
11
21
31
41
51
6
R1
35
33
R0
C135
C137 C138
C145
C142
C140
C122
C120
C146
C139
2A
1
OE
4Y
U1
4
SN
74
LV
C1
G1
25
DR
LR
R1
30
10
k0
JP6
C136
C123
2A
4
Y
1
OE
U1
2
SN
74L
VC
1G
12
6DR
LR
R1
47
49
R9
R1
48
49
R9
R1
52
49
R9
R1
28
49
R9
R1
50
49
R9
R1
51
49
R9
TP
96
TP
95
[2,6
]U
SB
I_S
CL
[2,6
]U
SB
I_C
OU
T
[2,6
]U
SB
I_S
DA
EI3
_IO
VD
DIO
VD
D
[8]
EI3
_D
SD
AT
A1
[8]
EI3
_D
SD
AT
A2
[8]
EI3
_D
SD
AT
A3
[8]
EI3
_D
SD
AT
A4
[8]
EI3
_D
SD
AT
A5
[8]
EI3
_D
SD
AT
A6
[8]
EI3
_D
SD
AT
A7
[8]
EI3
_D
SD
AT
A8
EI3
_IO
VD
DIO
VD
D
[8]
EI3
_S
CL
[8]
EI3
_S
DA
EI3
_IO
VD
DIO
VD
D
IOV
DD
EI3
_IO
VD
D
[6]
US
BI_
5V
00
EI3
_S
PI_
EN
[5]
INT
F_
DL
RC
LK
[5]
INT
F_
DB
CL
K
IOV
DD
IOV
DD
IOV
DD
EI3
_IO
VD
D
[8]
EI3
_D
LR
CL
K0
[8]
EI3
_D
BC
LK
0[8
]E
I3_
DB
CL
K1
[8]
EI3
_D
BC
LK
2[8
]E
I3_
DB
CL
K3
[8]
EI3
_D
LR
CL
K1
[8]
EI3
_D
LR
CL
K2
[8]
EI3
_D
LR
CL
K3
[5]
INT
F_
DS
DA
TA
8[5]
INT
F_
DS
DA
TA
7[5]
INT
F_
DS
DA
TA
6[5]
INT
F_
DS
DA
TA
5[5]
INT
F_
DS
DA
TA
4[5]
INT
F_
DS
DA
TA
3[5]
INT
F_
DS
DA
TA
2[5]
INT
F_
DS
DA
TA
1
[7,8
]
EI3
_M
CL
K
[6]
EI3
_M
CL
KI
[7,8
]E
I3_
MC
LK
[7]
MC
LK
_S
EL
[7]
MC
LK
_S
EL
EI3
_IO
VD
D
[7]
MC
LK
_S
EL
EI3
_IO
VD
DE
I3_
IOV
DD
[8]
EI3
_C
CL
K
[2,6
]U
SB
I_C
CL
K
[8]
EI3
_C
DA
TA
[8]
EI3
_C
LA
TC
H_
A
[8]
EI3
_C
LA
TC
H_
B
[8]
EI3
_C
LA
TC
H_
C
[2,6
]U
SB
I_C
LA
TC
H_
A
[2,6
]U
SB
I_C
DA
TA
[6]
EI3
_M
CL
KO
[8]
EI3
_C
OU
T
US
BI_
CL
AT
CH
_B
US
BI_
CL
AT
CH
_C
11588-026
Figure 26. Schematic, Page 7—Level Shift and Clock Direction Control
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 18 of 63
EI3
1A
SP
OR
T1
_D0
SP
OR
T1_
D1
SP
OR
T1
_CL
K
SP
OR
T1_
FS
SP
OR
T0_
D1
SP
OR
T0
_D0
SP
OR
T0_
FS
SP
OR
T0
_CL
K
SP
I0_
SE
L_
A
SP
I0_
MIS
O
SP
I0_
MO
SI
SP
I0_
CL
K
SD
A0'
SC
L0'
RE
SE
T_O
UT
'
DA
U_
MC
LK
SP
I0_
SE
L_
B
SP
I0_
SE
L_
C
R1
33
OP
EN
1 2 3 4 5 6 7 8 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
16
06
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
11
0
11
1
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
12
0
J6
HIR
OS
E_
FX
8-1
20
S-S
V(2
1)_
SO
CK
ET
D9 S
ch
ott
ky
R1
31
49
R9
EI3
_IO
VD
D
5V
0D
D
[7]
EI3
_S
CL
[7]
EI3
_S
DA
[7]
EI3
_D
SD
AT
A1
[7]
EI3
_D
SD
AT
A2
[7]
EI3
_D
SD
AT
A3
[7]
EI3
_D
SD
AT
A4
[7]
EI3
_C
LA
TC
H_
A
[7]
EI3
_C
DA
TA
[7]
EI3
_C
CL
K
[7]
EI3
_C
OU
T
[6]
MR
[7]
EI3
_D
LR
CL
K0
[7]
EI3
_D
BC
LK
0
[7]
EI3
_D
LR
CL
K1
[7]
EI3
_D
BC
LK
1
[7]
EI3
_M
CL
K
[7]
EI3
_C
LA
TC
H_
B
[7]
EI3
_C
LA
TC
H_
C
EI3
1B
SP
OR
T3_
D0
SP
OR
T3
_D1
SP
OR
T3
_CL
K
SP
OR
T3
_FS
SP
OR
T2
_D1
SP
OR
T2_
D0
SP
OR
T2
_FS
SP
OR
T2
_CL
K
SD
A0'
SC
L0
'
RE
SE
T_
OU
T'
1 2 3 4 5 6 7 8 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
16
06
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
11
0
11
1
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
12
0
J8
HIR
OS
E_
FX
8-1
20
S-S
V(2
1)_
SO
CK
ET
R1
56
OP
EN
+C
13
2
47
uF
5V
0D
D
EI3
_IO
VD
D
[7]
EI3
_D
SD
AT
A5
[7]
EI3
_D
SD
AT
A6
[7]
EI3
_D
SD
AT
A7
[7]
EI3
_D
SD
AT
A8
[7]
EI3
_D
LR
CL
K2
[7]
EI3
_D
LR
CL
K3
[7]
EI3
_D
BC
LK
2
[7]
EI3
_D
BC
LK
3
11588-027
Figure 27. Schematic, Page 8—SDP Interface Connectors
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 19 of 63
Error
Hig
h
No
rm
On
Off
RE
RR
NV
ER
R
ER
RO
RS
EM
PH
PH
DE
T R
AT
E
ValidAudio
>88kHz
MA
ST
ER
SL
AV
E
SE
RIA
L P
OR
T C
on
tro
l
128
xF
s
256
xF
s
RM
CK
Fre
q|--
----
-- S
ER
IAL
PO
RT
Fo
rma
t --
----
-|
SF
SE
L [
1:0
]
00
= L
J 2
4b
it0
1 =
I2S
24
bit
10
= R
J 2
4b
it1
1 =
Dir
ect
AE
S
1 0
1 0
SF
SE
L1S
FS
EL
0
C6
10n
F
C5
10n
F
C12
C4
L4
D4
RedDiffused
R3
392
R
D3
GreenDiffused
R2
392
R
L1
C11
0
11A2 1Y
U3-A
74HC04D-T
32A4 2Y
U3-B
74HC04D-T
53A6 3Y
U3-C
74HC04D-T
4R
XP
0
5R
XN
8F
ILT
6 VA
23 V
D
26S
DO
UT
28O
LR
CK
27O
SC
LK
24R
MC
K
10
RX
SE
L1
11
RX
SE
L0
12
TX
SE
L1
13
TX
SE
L0
19C
18U
17R
CB
L14
NV
/RE
RR
15
AU
DIO
3R
XP
12
RX
P2
1R
XP
3
20T
X
169
6K
HZ
21 V
L
9R
ST
25O
MC
K
7
AG
ND
22
DG
ND
U2
CS
841
6
C2
22n
F
C3
1.0
nF
R6
3k
01
C11
R12
5
47
k5
94A8 4Y
U3-D
74HC04D-T
115A10 5Y
U3-E
74HC04D-T
136A12 6Y
U3-F
74HC04D-T
D2
YellowDiffused
R1
392
R
R1
115
0R
R1
21
50R
R2
11
50R
R10
150
R
+C
10
10u
F
De
fau
ltRS
6
47k
5
De
fau
ltRS
547
k5
2
GN
D
3 DV
DD
1O
UT
U1
TO
RX
147
L(F
T)
L3
C112
R4
10k
0
12
3 45
6
S1
DP
DT
Slid
e
J1
CT
P-0
21
A-S
-YE
L
R5
75R
0
R2
0
10k
0
R9
10k
0
Def
au
ltRS
24
7k5
De
fau
ltRS
4
47
k5
De
fau
ltRS
14
7k5
Def
au
ltRS
347
k5
De
fau
ltRS
747
k5
IOV
DD
[5]
841
6_S
DA
TA [5
]84
16_
LR
CL
K [5]
841
6_
BC
LK
[6]
841
6_
MC
LK
I
IOV
DD
3V
3D
D
[2,6
]P
U_
RS
T
IOV
DD
IOV
DD
IOV
DD
IOV
DD
3V
3D
D
[6]
OM
CK
_F
EE
D
11588-028
Figure 28. Schematic, Page 9—S/PDIF Receiver
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 20 of 63
3v3
Lin
ear
Su
pp
ly
5v0
Sw
itch
ing
Su
pp
ly
+12
VD
C M
AX
GN
D
Pla
ne
dec
ou
plin
g
C1
17
C1
16
C1
14
47
uF
C1
08
C1
05
+C
11
94
7u
F
D1
TP
88
TP
2
L2
60
0 O
hm
@ 1
00
MH
z
L5
60
0 O
hm
@ 1
00
MH
z
C1
+C
10
74
7u
F
+C
11
84
7u
F
TP
8
TP
9
R1
3
47
5R
D5
Gre
en
Dif
fus
ed
R1
84
75
R
D6
GreenDiffused
TP
60
TP
86
TP
92
TP
5T
P1
TP
3T
P1
7T
P6
TP
4T
P1
3T
P5
6T
P2
3T
P9
4T
P3
6
2 13
J1
3
R1
24
24
3R
+C
11
5
10
uF
3O
UT
1
AD
J
2IN
U9
LM
31
7M
DT
R1
23
40
2R
7G
ND
8IN
6S
D
4F
B
1S
WIT
CH
2B
OO
ST
3B
IAS
5C
OM
P
U8
AD
P3
05
0A
RZ
C1
06
68
nF
C1
04
39
0p
F
R1
20
1k
15
R1
21
10
k2
R1
22
32
k4
D8
BA
T5
4T
1G
C1
09
0.4
7u
F
C1
13
47
uF
12
L6
22
uH
MS
S1
27
78
-22
3M
LB
D7
1N
58
19
HW
-7-F
R1
4
0R
00
R1
5
0R
00
C1
52
C1
54
C1
21
C1
43
TP
15
TP
14
TP
10
6T
P1
05
TP
10
2T
P1
04
5V
0D
D
3V
3D
D
+1
2V
DC
3V
3D
D
5V
0D
D
IOV
DD
AV
DD
11588-029
Figure 29. Schematic, Page 10—Power Supply
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 21 of 63
115
88-
03
0
Figure 30. Top Assembly
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 22 of 63
115
88
-03
1
Figure 31. Top Layer Copper
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 23 of 63
115
88
-03
2
Figure 32. L2 Ground
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 24 of 63
115
88
-033
Figure 33. L3 Power
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 25 of 63
1158
8-0
34
Figure 34. Bottom Copper
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 26 of 63
115
88
-03
5
Figure 35. Bottom Assembly
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 27 of 63
BILL OF MATERIALS—REVISION A PCB Table 2. Qty Reference Description Manufacturer Part Number Vendor Vendor Order # 1 U6 Multibit Σ-Δ DAC Analog Devices ADAU1962AWBSTZ or
ADAU1966AWBSTZ Analog Devices
ADAU1962AWBSTZ or ADAU1966AWBSTZ
1 J12 10-way shroud, polarized header
3M N2510-6002RB Digi-Key MHC10K-ND
1 U5 12.288 MHz, fixed SMD oscillator, 3.3 V to 5 V dc
Cardinal Components
CPPFX C 7 L T-A7 BR-12.288MHz TS
Cardinal Components
CPPFX C 7 L T-A7 BR-12.288MHz TS
2 J6, J8 120-pin socket, 0.6 mm Hirose Electric FX8-120S-SV(21) Digi-Key H1219-ND 1 U1 15 Mbps fiber optic
receiving module with shutter
Toshiba TORX147L(FT) Digi-Key TORX147LFT-ND
1 U2 192 kHz dgtl rcvr, 28-TSSOP
Cirrus Logic CS8416-CZZ Digi-Key 598-1124-5-ND
10 JP1, JP3 to JP9, JP11, JP21
2-pin header, unshrouded, jumper ,0.10"; use Tyco 881545-2 shunt
Sullins Electronics Corp
PBC02SAAN or cut down PBC36SAAN
Digi-Key S1011E-02-ND
1 U8 200 kHz, 1A, buck regulator
Analog Devices ADP3050ARZ Digi-Key ADP3050ARZ-R7CT-ND
1 J11 28-way, unshrouded 3M PBC14DAAN, or cut down PBC36DAAN
Digi-Key S2011E-14-ND
1 U9 3-term adj voltage regulator DPAK
ST Microelectronics
LM317MDT-TR Digi-Key 497-1574-1-ND
11 JP2, JP10, JP12 to JP20 3-pos SIP header Sullins PBC03SAAN or cut down PBC36SAAN
Digi-Key S1011E-03-ND
1 JP22 3-pos T-header Sullins PBC03SAAN or cut down PBC36SAAN
Digi-Key S1011E-03-ND plus single pin
1 J5 8-way, unshrouded, header dual row
Sullins Electronics Corp
PBC04DAAN or cut down PBC36DAAN
Digi-Key S2011E-04-ND or cut down S2011E-36-ND
27 C9 to C10, C14, C16, C22, C32, C39,C49, C55, C62, C74, C80, C83, C89, C91, C93, C95, C11, C125 to C131, C133 to C134
Alum electrolytic capacitor, FC 105°, SMD_B, 10 μF
Panasonic EC EEE-FC1C100R Digi-Key PCE3995CT-ND
4 C107, C118 to C119, C132
Alum electrolytic capacitor, FC 105°, 47 μF, SMD_D
Panasonic EC EEE-FC1C470P Digi-Key PCE4000CT-ND
3 U4, U14, U18 Buffer 3-state, single gate Texas Instruments SN74LVC1G125DRLR Digi-Key 296-18012-1-ND 1 Y1 Crystal, 12.288 MHz, SMT,
18 pF Abracon Corp ABM3B-12.288MHZ-10-1-U-T Digi-Key 300-8198-1-ND
4 L1, L3 to L4, L7 Chip ferrite bead, 600 Ω @ 100 MHz
TDK Corp MMZ1005S601C Digi-Key 445-2162-1-ND
2 L2, L5 Chip ferrite bead, 600 Ω @ 100 MHz
Steward HZ0805E601R-10 Digi-Key 240-2399-1-ND
3 R1 to R3 Chip resistor, 1%, 100 mW, thick film, 0603, 392R
Rohm MCR03EZPFX3920 Digi-Key RHM392HCT-ND
1 R5 Chip resistor, 1%, 100 mW thick film, 0603, 75R0
Panasonic EC ERJ-3EKF75R0V Digi-Key P75.0HCT-ND
2 R13, R18 Chip resistor, 1%, 475R, 125 mW, thick film, 0603
Panasonic EC ERJ-3EKF4750V Digi-Key P475HCT-ND
7 RS1 to RS7 Chip resistor, 1%, 47k5, 125 mW, thick film, 0603
Panasonic EC ERJ-3EKF4752V Digi-Key P47.5KHCT-ND
1 R126 Chip resistor, 100k, 1%, 63 mW, thick film, 0402
Rohm MCR01MZPF1003 Digi-Key RHM100KLCT-ND
14 R4, R9, R20, R46, R127, R130, R134, R137 to R140, R144, R149, R157
Chip resistor, 1%, 10k0, 63 mW, thick film, 0402
Rohm MCR01MZPF1002 Digi-Key RHM10.0KLCT-ND
1 R121 Chip resistor, 1%, 10k2, 63 mW, thick film, 0402
Vishay/Dale CRCW040210K2FKED Digi-Key 541-10.2KLCT-ND
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 28 of 63
Qty Reference Description Manufacturer Part Number Vendor Vendor Order # 5 R10 to R12, R21, R49 Chip resistor, 1%, 150 R,
63 mW, thick film, 0402 Rohm MCR01MZPF1500 Digi-Key RHM150LCT-ND
1 R120 Chip resistor, 1%, 1k15, 63 mW, thick film, 0402
Panasonic EC ERJ-2RKF1151X Digi-Key P1.15KLCT-ND
2 R56, R146 Chip resistor, 1%, 1k50, 63 mW, thick film, 0402
Panasonic EC ERJ-2RKF1501X Digi-Key P1.50KLCT-ND
1 R50 Chip resistor, 1%, 1M00, 63 mW, thick film, 0402
Rohm MCR01MZPF1004 Digi-Key RHM1.00MLCT-ND
1 R124 Chip resistor, 1%, 243R, 63 mW, thick film, 0402
Vishay/Dale CRCW0402243RFKED Digi-Key 541-243LCT-ND
1 R122 Chip resistor, 1%, 32k4, 63 mW, thick film, 0402
Vishay/Dale CRCW040232K4FKED Digi-Key 541-32.4KLCT-ND
5 R59, R62 to R63, R66, R141
Chip resistor, 1%, 33R2, 63 mW, thick film, 0402
Panasonic EC ERJ-2RKF33R2X Digi-Key P33.2LCT-ND
3 R6, R111, R155 Chip resistor, 1%, 3K01, 63 mW, thick film, 0402
Rohm MCR01MZPF3011 Digi-Key RHM3.01KLCT-ND
2 R25, R145 Chip resistor, 1%, 3k32, 63 mW, thick film, 0402
Vishay/Dale CRCW04023K32FKED Digi-Key 541-3.32KLCT-ND
1 R123 Chip resistor, 1%, 402R, 63 mW, thick film, 0402
Vishay/Dale CRCW0402402RFKED Digi-Key 541-402LCT-ND
16 R31, R33, R35, R37, R44, R51, R57, R64, R70, R76, R82, R88, R91, R93, R95, R97
Chip resistor, 1%, 475R, 63 mW, thick film, 0402
Stackpole RMCF0402FT475R Digi-Key RMCF0402FT475RCT-ND
1 R125 Chip resistor, 1%, 47k5, 63 mW, thick film, 0402
Rohm MCR01MZPF4752 Digi-Key RHM47.5KLCT-ND
16 R8, R22, R26, R29, R45, R52, R58, R65, R71, R77, R83, R89, R100, R102 R104, R106
Chip resistor, 1%, 49k9, 63 mW, thick film, 0402
Vishay/Dale CRCW040249K9FKED Digi-Key 541-49.9KLCT-ND
15 R24, R38, R42, R53, R128 to R129, R131 to R132, R142 to R143, R147 to R148, R150 to R152
Chip resistor, 1%, 49R9, 63 mW, thick film, 0402
Rohm MCR01MZPF49R9 Digi-Key RHM49.9LCT-ND
1 R27 Chip resistor, 1%, 562R, 63 mW, thick film, 0402
Vishay/Dale CRCW0402562RFKED Digi-Key 541-562LCT-ND
8 R67, R72 to R73, R78 to R79, R84 to R85, R90
Chip resistor, 1%, 68R1, 63 mW, thick film, 0402
Rohm MCR01MZPF68R1 Digi-Key RHM68.1LCT-ND
18 R39, R43, R107, R117 to R119, R158 to R161, R170 to R177
Chip resistor, 5%, 0R00, 100 mW, thick film, 0402
Panasonic ECG ERJ-2GE0R00X Digi-Key P0.0JCT-ND
2 R14 to R15 Chip resistor, 5%, 0R00, 125 mW, thick film, 0805
Panasonic EC ERJ-6GEY0R00V Digi-Key P0.0ACT-ND
1 S1 DPDT slide switch vertical E-Switch EG2207 Digi-Key EG1940-ND 48 R7, R19, R23, R28, R30,
R32, R34, R36, R40 to R41, R47, to R48, R54 to R55, R60 to R61, R68 to R69, R74 to R75, R80 to R81, R86 to R87, R92, R94, R96, R98 to R99, R101, R103, R105, R108 to R110, R112 to R116, R162 to R169
Open Open
2 R133, R156 Open Open 32 TP7, TP10 to TP12,
TP16, TP18 to TP19, TP22, TP24, TP37, TP40, TP42, TP47, TP49, TP52, TP55, TP65, TP68, TP70, TP73, TP75, TP77, TP87, TP89 to TP91, TP93,
Open Open
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 29 of 63
Qty Reference Description Manufacturer Part Number Vendor Vendor Order # TP97 to TP101
3 D3, D5 to D6 Green diffused, 10 millicandela, 565 nm 1206
Lumex Opto SML-LX1206GW-TR Digi-Key 67-1002-1-ND
1 U11 IC 2-bit, dual bus, TXRX 8-SSOP
Texas Instruments SN74LVC2T45DCTR DigiKey 296-16845-1-ND
3 U13, U16 to U17 IC 8-bit, dual bus, TXRX 24-SSOP
Texas Instruments SN74LVCH8T245DBR DigiKey 296-21067-1-ND
1 U15 IC I2C bus, repeater 8-TSSOP
NXP Semiconductor
PCA9517DP-T DigiKey 568-1829-2-ND
1 U3 IC inverter, hex TTL/LSTTL 14 SOIC
NXP Semiconductor
74HC04D-T DigiKey 568-1384-1-ND
1 J13 Mini power jack, 0.08" R/A TH
Switchcraft, Inc. RAPC722X Digi-Key SC1313-ND
32 TP1 to TP6, TP8 to TP9, TP13 to TP15, TP17, TP20 to TP21, TP23, TP25, TP27, TP36, TP38, TP44 to TP45, TP56, TP60, TP71, TP86, TP88, TP92, TP94, TP102, TP104 to TP106
Mini test point, white .1" OD
Keystone Electronics
5002 Digi-Key 5002K-ND
2 C113 to C114 Multilayer ceramic, 47 μF, 10 V, X5R, 1206
Kemet C1206C476M8PACTU Digi-Key 399-5508-6-ND
44 C1, C4, C7, C11 to C12, C27, C33, C36 to C37, C40 to C42, C44, C47, C53, C65, C67 to C68, C71, C75, C77, C105, C108, C110 to C112, C116 to C117, C120 to C123, C135 to C140, C142 to C143, C145 to C146, C152, C154
Multilayer ceramic, 0.10 μF, 16 V, X7R, 0402
Murata ENA GRM155R71C104KA88D Digi-Key 490-3261-1-ND
5 C43, C45, C72, C76, C109
Multilayer ceramic, 47 μF, 16 V, X7R, 0603
Taiyo Yuden EMK107B7474KA-T Digi-Key 587-1250-1-ND
2 C5 to C6 Multilayer ceramic, 10 nF, 25 V, NP0, 0603
TDK Corp C1608C0G1E103J Digi-Key 445-2664-1-ND
1 C20 Multilayer ceramic, 5.6 nF, 25 V, NP0, 0603
TDK Corp C1608C0G1E562J Digi-Key 445-2666-1-ND
1 C2 Multilayer ceramic, 22 nF, 25 V, NP0, 0805
Murata ENA GRM21B5C1H223JA01L Digi-Key 490-1644-1-ND
2 C28, C124 Multilayer ceramic, 10 pF, 50 V, NP0, 0402
Kemet C0402C100J5GACTU Digi-Key 399-1011-1-ND
3 C50, C52, C141 Multilayer ceramic, 2.2 pF, 50 V, NP0, 0402
Johanson Technology
500R07S2R2BV4T Digi-Key 712-1279-1-ND
2 C29, C34 Multilayer ceramic, 22 pF, 50 V, NP0, 0402
Murata ENC GRM1555C1H220JZ01D Digi-Key 490-1283-1-ND
2 C17, C104 Multilayer ceramic, 390 pF, 50 V, NP0, 0402
Murata ENA GRM1555C1H391JA01D Digi-Key 490-1296-1-ND
8 C56 to C58, C60, C63 to C64, C66, C70
Multilayer ceramic, 4.7 pF, 50 V, NP0, 0402
Johanson Technology
500R07S4R7BV4T Digi-Key 12-1166-1-ND
1 C18 Multilayer ceramic, 2.2 nF, 50 V, NP0, 0603
Murata Electronics
GRM1885C1H222JA01D Digi-Key 490-1459-1-ND
1 C3 Multilayer ceramic, 1.0 nF, 50 V, NP0, 0603
Panasonic EC ECJ-1VC1H102J Digi-Key PCC2151CT-ND
16 C23 to C-26, C31, C38, C48, C54, C61, C73, C79, C82, C84 to C87
Multilayer ceramic, 2.7 nF, 50 V, NP0, 0603
Murata ENA GRM1885C1H272JA01D Mouser 81-GRM185C1H272JA01D
1 C106 Multilayer ceramic, 68 nF, 50 V, NP0, 1206
Murata GCM31C5C1H683JA16L Digi-Key 490-5323-1-ND
1 C21 Multilayer ceramic, 39 nF, 50 V, X7R, 0805
Panasonic EC ECJ-2VB1H393K Digi-Key PCC1835CT-ND
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 30 of 63
Qty Reference Description Manufacturer Part Number Vendor Vendor Order # 16 C8, C13, C15, C19, C30,
C35, C46, C51, C59, C69, C78, C81, C88, C90, C92, C94
10 μF, not fitted Panasonic EC EEE-FC1C100R Digi-Key PCE3995CT-ND
1 JP23 2 jumper, not fitted Sullins Electronics Corp
PBC02SAAN or cut down PBC36SAAN
Digi-Key S1011E-02-ND
1 Q1 PNP transistor Zetex, Inc. ZX5T953GTA Digi-Key ZX5T953GCT-ND 1 J1 RCA jack, PCB TH mount,
R/A yellow Connect-Tech Products Corp.
CTP-021A-S-YEL Connect-Tech
CTP-021A-S-YEL
1 D4 Red diffused, 6.0 millicandela, 635 nm 1206
Lumex Opto SML-LX1206IW-TR Digi-Key 67-1003-1-ND
2 R135 to R136 Resistor network, isolated 8 res, 33R0
CTS Corp. 741X163330JP Digi-Key 741X163330JPCT-ND
2 J2, J4 SMA receptacle, straight PCB mount
Amp-RF Division 901-144-8RFX Digi-Key ARFX1231-ND
1 L6 SMT power inductor, 22 μH Coilcraft MSS12778-223MLB Coilcraft MSS12778-223MLB 1 U12 Sngl bus, buff gate, 3ST
SOP-5 Texas Instruments SN74LVC1G126DRLR DigiKey 296-18013-1-ND
1 D8 Schottky 30 V, 0.2 A, SOD123 diode
On Semiconductor
BAT54T1G Digi-Key BAT54T1GOSCT-ND
2 D9 to D10 Schottky 30 V, 0.5 A, SOD123 diode
On Semiconductor
MBR0530T1G Digi-Key MBR0530T1GOSCT-ND
1 D7 Schottky 40 V, 1 A, SOD123 diode
Diodes, Inc 1N5819HW-7-F Digi-Key 1N5819HW-FDICT-ND
8 J3, J9 to J10, J14 to J18 Sterero mini jack SMT CUI, Inc. SJ-3523-SMT Digi-Key CP-3523SJCT-ND 1 D1 TVS Zener 15 V, 600 W
SMB ON Semiconductor
1SMB15AT3G Digi-Key 1SMB15AT3GOSCT-ND
1 S2 Tact switch, 6 mm, gull wing, SPST-NO
Tyco/Alcoswitch FSM6JSMA Digi-Key 450-1133-ND
1 D2 Yellow diffused, 4.0 millicandela, 585 nm 1206
CML Innovative Tech
CMD15-21VYD/TR8 Digi-Key L62307CT-ND
1 U10 Microprocessor voltage supervisor, logic low RESET output
Analog Devices ADM811RARTZ-REEL7 Analog Devices
ADM811RARTZ-REEL7
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 31 of 63
FUNCTIONAL BLOCK DIAGRAM—REVISION B PCB
DAC 1-16
SPDIF
INTERFACE POWER SUPPLY
CONTROLINTERFACE
SDPINTERFACE
ADAU196XA
CLOCK &DATA
ROUTING
MCLKSELECTEXTERNAL
DATA AND CLOCKINTERFACE
Figure 36.
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
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SETTING UP THE EVALUATION BOARD—REVISION B PCB STANDALONE MODE The ADAU196xA has a standalone mode, which allows the user to choose between a limited number of operation modes without the need for a control interface. Turning on Section 4 of Switch S9, as shown in Figure 37, pulls the SA_MODE (Pin 46) high, enabling standalone mode in the ADAU196xA. The SA_MODE selections are listed in Table 3.
Table 3. Standalone Modes Pin Setting Description Pin 42 0 Master serial audio interface 1 Slave serial audio interface Pin 43 0 256 × fS 1 384 × fS Pin 44 0 Reserved, set to 0 Pin 45 0 I2S mode 1 TDM mode Pin 32 to Pin 31 00 TDM4, pulse 01 TDM8, pulse 10 TDM16, pulse 11 TDM8, 50% duty
On the EVAL-ADAU196xAZ, each of the four control port pins of the ADAU196xA are brought out to six DIP switches, allowing the user to assign each pin to either ground or IOVDD. In standalone mode, these switches connect the individual pins to high (IOVDD) or low (GND) to put the ADAU196xA in the desired mode.
12 C1
C2
C3
C4
34 12 C1
C2
C3
C4
34
Figure 37. Standalone Mode
The EVAL-ADAU196xAZ arrives configured for S/PDIF input. The S/PDIF receiver operates as a clock master, putting out an I2S stream at 256 × fS. For quick startup, the ADAU196xA is in standalone mode with the settings shown in Figure 38.
Pin 42 is pulled high (1) and Pin 43 to Pin 45 are pulled low (0). According to Table 3, this puts the ADAU196xA in slave mode, running at 256 × fS, and the audio serial port in I2S mode.
12 C1
C2
C3
C4
34 12 C1
C2
C3
C4
34
Figure 38. Standalone Mode, Slave Mode, I2S, 256 × fS
I2C AND SPI CONTROL The evaluation board can be configured for live control over the registers in the ADAU196xA. J4 is the I2C/SPI control port, as shown in Figure 39.
Figure 39. I2C/SPI Control Port, J4
The ADAU196xA can be controlled using either the SigmaStudio program or the Automated Register Window Builder software. The included USBi control interface is plugged into J4, enabling the software to control the ADAU196xA. For this configuration, the ADAU196xA can be assigned to I2C mode using Address 00. I2C mode is the default and is normally used. See Figure 40 for the correct jumper positions.
12 C1
C2
C3
C4
34 12 C1
C2
C3
C4
34 12 C1
C2
Figure 40. ADAU196xA I2C Control, Address 00
The Automated Register Window Builder controls the ADAU196xA and is available for download at www.analog.com/ADAU1962A or www.analog.com/ADAU1966A.
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
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The ADAU196xA can also be put in SPI mode for control using a Serial Peripheral Interface (SPI). See Figure 41 for the correct jumper positions.
12 C1
C2
C3
C4
34 12 C1
C2
C3
C4
34 12 C1
C2
Figure 41. ADAU196xA SPI Control
SIGMASTUDIO SOFTWARE INSTALLATION The SigmaStudio program offers live control of the ADAU196xA using a graphical interface. Multiple parts can be controlled on one PCB using the USBi interface. SigmaStudio downloads can be found at www.analog.com/SigmaStudio.
Additional installation instructions can be found at the SigmaStudio Installation Procedures page on the Analog Devices Wiki.
There is only one graphical control GUI file for the entire family of ADAU196xA (ADAU1966A and ADAU1962A) and ADAU196x (ADAU1966 and ADAU1962) devices. Drag and drop in the ADAU1966 GUI and connect it to the USBi, as shown in Figure 42.
Figure 42. SigmaStudio GUI Interface for the ADAU196x/ADAU196xA Family
When the GUI loads, a control tab for the ADAU196xA appears in the lower part of the window. Select the control tab to bring forward the controls for the device. There is no need to compile and/or download and program, because this device has no DSP. Control is live immediately after connecting the GUI to the USBi GUI (see Figure 43).
Figure 43. ADAU196xA Register Control Window
AUTOMATED REGISTER WINDOW BUILDER SOFTWARE INSTALLATION The Automated Register Window Builder is a program that launches a graphical interface for direct, live control of the ADAU196xA registers. The GUI content for a specific device is defined in a device-specific .xml file; these files are included in the software installation.
To install the Automated Register Window Builder software, follow these steps:
5. Go to www.analog.com/ADAU1962A or www.analog.com/ADAU1966A and download the ARWBvXX.zip file from the product page.
6. Open the downloaded ARWBvXX.zip file and extract the files to an empty folder on your PC.
7. Install the Automated Register Window Builder by double-clicking setup.exe and following the prompts. A PC restart is not required.
8. Copy the .xml file for the ADAU196xA from the extraction folder into the folder C:\ProgramFiles\Analog Devices Inc\ AutomatedRegWin, if it is not already installed.
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HARDWARE SETUP—USBi To set up the USBi hardware, follow these steps:
4. Plug the USBi ribbon cable into the J4 I2C/SPI port. 5. Connect the USB cable to your PC and to the USBi. 6. When prompted for drivers,
a. Choose Install from a list or a specific location. b. Choose Search for the best driver in these locations. c. Check the box for Include this location in the search. d. Find the USBi driver C:\Program Files\Analog
Devices Inc\AutomatedRegWin\USB drivers. e. Click Next. f. If prompted to choose a driver, select CyUSB.sys. g. If the PC is running Windows® XP and a message
appears stating that the software has not passed Windows logo testing, click Continue Anyway.
The user can now open the Automated Register Window Builder application and load the .xml file for the device on the evaluation board. Plug the 10-way ribbon cable on the USBi into the I2C/SPI port (J4) on the evaluation board.
POWERING THE BOARD The EVAL-ADAU196xAZ evaluation board requires a power supply input of 5 V to 6 V dc and ground to the power jack.
The on-board regulators provide the 3.3 V rails. The 5 V to 6 V input supplies the 3.3 V power supply and other peripherals via the R13 system development platform (SDP) interface optional resistor. To supply this power, install a 0 Ω jumper in place of R13. To supply power to this evaluation board from the SDP interface, install a 0 Ω jumper into the location for R146. The 3.3 V rail is derived from the 5 V supply by an LDO linear regulator; it provides voltage to AVDD and IOVDD as well as other active peripherals.
AVDD, DVDD, and IOVDD are connected to the ADAU196xA using unpopulated 2-pin headers with a trace on the bottom layer of the board shorting the pins. If the user needs to insert a different power source or measure current draw of the ADAU196xA, the user can cut the trace on the bottom of the PCB and either directly wire to the jumper holes or install header pins for JP7, JP8, or JP9.
Figure 44. AVDD and IOVDD Jumper Resistors
The ADAU196xA has an internal voltage regulator that allows the user to derive DVDD and PLLVDD from the AVDD voltage source. The external PNP transistor Q1 and the passives, C116, C11, C10, and R18, make the regulator circuit shown in Figure 45. To activate the circuit, all sections of Switch S2 must be in the on position. Power must be shut off to the board when changing these switches. To supply DVDD and PLLVDD from an external source, bypass this regulator by shutting off all sections of S2 and connect DVDD using TP22 or JP7, and PLLVDD using TP29. Note that the user must supply power to PLLVDD even if the PLL is disabled using the register settings.
To measure the DVDD current supplied to the device, using the internal voltage regulator, turn off only Section 4 of Switch S2. Then connect a current meter between the TP18 and TP22 test points. Remove power when making these connections to avoid damage to the board. This procedure only measures the DVDD current to the device, not the PLLVDD current.
To measure the PLLVDD current supplied to the device using the internal voltage regulator, remove R177 (0 Ω). Then connect a current meter between the TP18 and TP29 test points. All sections of Switch S2 remain on if only measuring the PLLVDD current. Remove power when making these connections to avoid damage to the board. This procedure only measures the PLLVDD current to the device, not the DVDD current.
To measure both the DVDD and PLLVDD, remove R177 and the jumper from TP29 to TP22 and measure the current at JP7, as described previously.
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
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Figure 45. ADAU196xA Internal Regulator Switches and Connections,
Shown with Switches in On State
RESETTING THE EVALUATION BOARD The EVAL-ADAU196xAZ has provisions for resetting and powering down the ADAU196xA. S1 on the evaluation board, shown in Figure 46, is a momentary reset switch that pulls the master reset (MR) line low; this line controls the reset generator, U11. MR is also connected to the USBi and the SDP interface connectors through steering diodes and protection resistors so that outside devices can control the reset state of the evaluation board. The power-down jumper (JP1) allows the MR line to be tied low to keep the board in a reset state. The MR line is also connected to a pin on the SDP interface through a steering diode and protection resistor (R134), allowing this board to be reset by an external reset signal. The output of the reset generator drives the PU/RST line.
The PU/RST line is directly connected to two devices: the S/PDIF receiver and the ADAU196xA.
Figure 46. Reset Switch (S1) and Power-Down Jumper (JP1)
SETTING UP THE MASTER CLOCK (MCLK) The MCLK routing, direction, oscillator enable and loop filter settings on the evaluation board are handled by DIP switches (S8), allowing any one of four sources to be selected: S/PDIF, the crystal (XTAL), an active oscillator (OSC), and the SDP standard development platform/external interface (INTF/EXT) connector. The switches are shown in Figure 47.
ON
1 2 3 4 5 6 7 8
CTS
902
Figure 47. MCLK Source Select Switches
Switch 1 to Switch 4 of DIP switch (S8) selects the source of MCLK for the ADAU196xA. Only one switch at a time must be on. There is no damage to the board if more than one source is selected; however, the board does not function properly. The evaluation board arrives with MCLK from the S/PDIF interface selected as the default. The evaluation board has a 12.288 MHz active oscillator that can be selected by turning on S8-3. The active oscillator needs to be enabled by turning on Switch S8-5. There is also an on-board crystal oscillator that is selected by turning on Switch S8-1.
The evaluation board can be set to receive MCLK from the SDP interface connectors. To do so, turn on Switch S8-4. The MCLK line going to the SDP interface also has a 2-pin header that can be used to inject MCLK for an external source. It can also be used to monitor the MCLK input in addition to TP23. Note that TP23 is after all the level shifters; therefore, it is at the internal evaluation board signal levels. The external MCLK header (JP4) is shown in Figure 48. The square pin (Pin 1) is ground.
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
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Figure 48. External MCLK Header (JP4)
Switch S8-6 sets the direction of the MCLK signal. If S8-6 is on, the direction of the MCLK is an input to the board. If S8-6 is off, the direction is an output. The output is derived from the MCLKO pin of the ADAU196xA and goes through a level shifter. This signal is then fed back to the EXT MCLK signal line to the INTF/EXT SDP and header connections. Therefore, JP4 is an MCLK output and MCLK feeds the SDP interface connector. This MCLK is not fed to the S/PDIF interface. The S/PDIF is always a master for MCLK.
Note that MCLKO, the master clock output pin of the ADAU196xA, appears at TP12, CLKOUT. This signal is taken directly from the ADAU196xA and does not go through any level shifters or buffering. This test point is meant for use as a signal monitor only.
SELECTING THE PLL LOOP FILTER The PLL in the ADAU196xA is very flexible, allowing the device to run from a wide range of either MCLK or LRCLK frequencies.
It is also possible to shut the PLL off altogether and use the device in direct lock mode; functionality with no PLL is limited to MCLK = 512 × fS, for 48 kHz mode.
ON
1 2 3 4 5 6 7 8
CTS
902
Figure 49. MCLK Selection for PLL Loop Filter
By default, the ADAU196xA runs from the PLL using MCLK as the clock source. The MCLK loop filter must be selected by turning on S8-7, as shown in Figure 49.
LRCLK can be selected as the PLL clock source using the PLL and Clock Control 0 Register, Bits[7:6]. In this case, the LRCLK loop filter must be selected by turning on Switch S8-8. If LRCLK is selected as the PLL clock, there is no need for an MCLK.
Note that only one switch can be on at a time. If both are on or both are off, the PLL behavior is undefined.
ROUTING DIGITAL AUDIO CONNECTIONS The ADAU196xA evaluation board has three separate inputs for digital audio signals: the S/PDIF, the SDP interface, and the DSDATAx headers. The SDP and the headers are the same physical signal lines; therefore, the headers can serve as a test point to monitor signals from the SDP, and when the SDP is not in use, the headers can serve as an input for data.
The S/PDIF receiver uses an optical Toslink jack (U2), as shown in Figure 50.
Figure 50. S/PDIF Input Jack (U2)
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A series of resistors are provided on a three-pad footprint to set the functional mode of the S/PDIF receiver, as shown in Figure 51. Moving the 0 Ω jumper between the left two pads or the right two pads sets the pins to a low or a high. By default, the S/PDIF receiver runs in master mode, 256 × fS, I2S format. Consult the data sheet for the S/PDIF receiver to make the required changes to the hardware mode.
Figure 51. S/PDIF Mode Selection Resistors
The switches and header shown in Figure 52 control the routing for the S/PDIF receiver data and the signals from the header/SDP data to the eight DSDATAx lines of the ADAU1962A/ADAU1966A. S6 Section 2 selects the input to a buffer; the output of this buffer shows up on the left-hand side of Switch S4 and Switch S5.
Turning on the individual switch of S4 and S5 connects the corresponding DSDATAx signal from the header/SDP interface (J3) to the ADAU1962A/ADAU1966A. When the individual switches are turned off, the DSDATAx line of the ADAU1962A/ADAU1966A is connected to the output of a buffer. The input to the buffer is controlled by Switch S6-2. When S6-2 is off, it routes the DSDATA1 signal to the buffer. When S6-2 is on, it routes the S/PDIF signal to the buffer, making it available to all the data inputs. This is the only signal path into the ADAU1962A/ADAU1966A for the S/PDIF input.
The J3 header can be used as either a signal monitor connection of the signal from the SDP, or it can be used as an input if nothing is connected to the SDP interface. All of the odd numbered pins (Pin 1, Pin 3, Pin 5 … Pin 15) of J3 are connected to ground. There are level matching buffers between the J3 header and the ADAU196xA DSDATAx pins. See the Level Translators section for more details.
12
C1 C2
C3 C4
34
12
C1 C2
C3 C4
34
12
C1 C2
Figure 52. Data Routing
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L/R AND BIT CLOCK ROUTING S3 determines the source of the bit clock and the L/R clock lines of the ADAU1962A/ADAU1966A. Pin 1 to Pin 4, which correspond to Switch 1 to Switch 4, are connected to the DLRCLK pin of the ADAU1962A/ADAU1966A. Pin 5 to Pin 8 and Switch 5 to Switch 8 are connected to the DBCLK pin of the ADAU1962A/ADAU1966A. Note that the DBCLK pin is the bit clock pin, and DLRCLK is the L/R clock pin.
Both the DBCLK and the DLRCLK pins of the ADAU1962A/ ADAU1966A are bi-directional and are set using internal registers. It is up to the user to ensure that the register settings and the dip switch settings are compatible. No damage occurs if they are improperly set; however, the device does not function (see Figure 53). The terms Send and Return are used on the evaluation board and refer to the vantage point of the ADAU1962A/ADAU1966A. Therefore, a Send is an output from the ADAU1962A/ADAU1966A out of the evaluation board to an external PCB. The clocks are sent out to the EXT BCLK Out and EXT LRCLK Out headers, JP11 and JP12. A Return is an input to the evaluation board and the ADAU1962A/ADAU1966A. The clocks can be fed into the EXT BCLK In and EXT LRCLK In headers, JP2 and JP3. Therefore, when interfacing to the SDP or the external headers, the proper switch must be thrown to allow the ADAU1962A/ADAU1966A to be a master or a slave. When using the SDP, the external jumpers (JP2, JP3, JP11, and JP12) can be used as test points to monitor the clocks (see Figure 54). Pin 1 of these headers, the square pins, are connected to ground. The S/PDIF input is always the master; therefore, the ADAU1962A/ADAU1966A must always slave to the S/PDIF interface clocks.
ON 1
23
45
67
8
CT
S
902
Figure 53. L/R and Bit Clock Routing Switches
Figure 54. LRCLK and BCLK Headers
The SDP interfaces, J1 and J2, make up a standard interconnect within Analog Devices. They provide for the transfer of digital audio clocks and control between boards. See the pinout included in the schematic in Figure 65. Figure 55 shows the SDP interface connector. When a board is plugged into this connector, U16 is disabled and the external board supplies IOVDD to the level translators to allow proper levels to the external board. See the Level Translators section for more details.
Figure 55. SDP Interface
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 39 of 63
LEVEL TRANSLATORS This evaluation board supplies 3.3 V as IOVDD for the level translators if there is no external board plugged into the SDP platform. The levels at the data and clocking headers are at the 3.3 V level by default. U16 controls the IOVDD power to the level translators. U16 is disabled when a board is plugged into the SDP platform, placing the output in a high-Z state, allowing the external IOVDD from Pin 116 of J1 to power up the level converters.
If the user chooses to use the headers to interface to the EVAL-ADAU196xAZ and requires a different IOVDD, U16 needs to be manually disabled. Shorting the two pins of JP5 together disables the output of U16. Then the user can inject IOVDD using JP6. Pin 1 of JP6, the square pin, is ground. See Figure 56 for jumper locations.
R155 is a 0 Ω jumper that can be used for measuring IOVDD current flowing into U16. To use this function, R155 (0 Ω) must be removed and an ammeter inserted between the pins of R155. See the schematic diagrams for details. This does not measure the current when a board is plugged into the SDP platform.
Figure 56 External IOVDD for Level Translators
CONNECTING ANALOG AUDIO CABLES There are two forms of the analog outputs of the ADAU196xA evaluation board: differential and single ended.
The board comes standard with the single-ended outputs appearing on through-hole test points as well as on the TRS mini connectors.
The single-ended outputs of the ADAU196xA drive the connectors directly, through a simple 1-pole RC filter with appropriate ac coupling.
To evaluate the differential outputs, the user can modify the board to accomplish this with a little soldering and a few parts.
MODIFICATION FOR DIFFERENTIAL OUTPUT The ADAU196xA evaluation board can be modified to be used differentially.
See Figure 57 for the schematic of the standard filter. The reference designators shown in Figure 57 are not the reference designators on the actual evaluation board. They are there only as a reference in this document. See the schematic diagram for the proper designators used for each channel on the evaluation board. To modify for balanced operation, perform the following steps for each channel:
6. Remove R6 (0 Ω jumper). 7. Change R1 from 470 Ω to 237 Ω (0402). 8. Add R2 (237 Ω, 0402). 9. Add C3 (10 μf). 10. Add R4 (49.9 kΩ, 0402).
++
R1470Ω
R2OPEN R3
49.9kΩR4OPEN
R5OPEN
R60Ω
C12.7nF
C2
C3 OPEN
DACP
DACN
OUTP
OUTN
10µF
115
88
-01
9
Figure 57. Typical Evaluation Board Filter
MODIFICATION TO USE THE N OUTPUT The ADAU196xA evaluation board can be modified to use the DACN output instead of the DACP output. If the user needs to invert all the channels, it is recommended to do so in the software using the DAC CONTROL 2 Register or by inverting the I2S data stream.
See Figure 57 for the schematic of the standard filter. To modify to use the N output, perform the following steps for each channel:
6. Move R6 over to R5 (0 Ω jumper). 7. Move R1 over to R2 (470 Ω). 8. Move C2 over to C3 (10 μF). 9. Move R3 over to R4 (49.9 kΩ). 10. Install a jumper between the N and P output test points.
Note that if new parts are to be used for R2, R4, R5, and C3, then R1, R3, R6, and C2 must be removed.
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 40 of 63
SCHEMATICS AND ARTWORK—REVISION B PCB
ADAU196XA
DAC Diff Out 1-8 Passive RC 1 pole
DAC Diff Out 9-16 Passive RC 1 pole
Power Supply Regulators
3v3 = Linear Supply derived from 5v0
Int RegXistor
DVDDPLLVDD
AVDD = 3v3
IOVDD = 3v3
0 ohm jumpers for each supplyfor current measurement
MCLK SourcesSPDIF
CrystalSDP Intf /EXT In
Active OSC
USBi Control port
SA_Mode Sw
COM Port Sw
SPDIF Receiver
DSP/FPGA Interface
BCLK, LRCLKSDATA HEADERS
with Buffer
6 VDCInput
Optical
Allows for DirectConnect to DUT
Single Ended Outs on TRS Mini jacks
Reset Switch
3v3 for SPDIF CoreIOVDD comes from DUT IOVDD
Control JumpersHardware Mode
Desktop Supply
CM Output on TP
Buffered MCLKO
CLKs
CLKs and DATA
3v3 / 2v5
Single Ended Outs on TRS Mini jacks
SDP INTERFACE
Figure 58. Schematic, Page 1—EVAL-ADAU196xAZ Block Diagram
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 41 of 63
En
ab
le--
>
AD
AU
19
66
Vo
ltag
eR
egu
lato
r
MC
LKLR
CLK
<--
Dis
ab
le
C4
00
.47u
F
C38
0.1
0uF
C4
50.1
0uF
C4
40.1
0uFC4
10.1
0uF
C3
90
.47u
F
C4
30
.47u
F
C4
20
.47u
F
C3
40.1
0uF
C3
20.1
0uF
C30
0.1
0uF
C2
70.1
0uF
C3
30.1
0uF
C2
50.1
0uF
C2
90.1
0uF
C2
60.1
0uF
JP9
JP8
+C
132
10u
F
+C
131
10u
F
TP3
1TP
30
TP2
5
TP2
9
TP2
1
TP2
2
B
C
E
CQ1
ZX
5T9
53G
TA
C1
00.1
0uF
C1
10.1
0uF
+C
116
10u
F
R1
8
1k5
0
TP1
8
TP1
7
C1
27
2.2
nF
NP0
C1
28
39n
F
R1
80
3k3
2
C1
253
90p
F
C1
26
5.6
nF
R1
78
56
2R
+
C1
191
0uF +
C1
201
0uF
+
C1
23
10u
F
+
C1
29
10u
F
+
C1
241
0uF
+
C1
301
0uF
27
DB
CLK
28
DLR
CLK
31
DS
DA
TA8
32
DS
DA
TA7
33
DS
DA
TA6
34
DS
DA
TA5
35
DS
DA
TA4
36
DS
DA
TA3
37
DS
DA
TA2
38
DS
DA
TA1
30DGND
21DGND
19
MC
LKO
18
XTA
LO
17
MC
LKI/
XTA
LI
16
PLLV
DD
15
LF14
PLLG
ND
47
PU/R
ST
46
SA
_M
OD
E
45
CLA
TCH
/AD
DR
0
44
CC
LK/S
CL
43
CO
UT/
SD
A
42
CD
ATA
/AD
DR
1
50
DA
C1P
51
DA
C1N
52
DA
C2P
53
DA
C2N
54
DA
C3P
55
DA
C3N
56
DA
C4P
57
DA
C4N
59
DA
C_B
IAS
160
DA
C_B
IAS
2
64
DA
C5P
65
DA
C5N
66
DA
C6P
67
DA
C6N
68
DA
C7P
69
DA
C7N
70
DA
C8P
71
DA
C8N
72
DA
C9P
73
DA
C9N
74
DA
C1
0P75
DA
C1
0N76
DA
C1
1P77
DA
C1
1N78
DA
C1
2P79
DA
C1
2N
1D
AC
_B
IAS
32
DA
C_B
IAS
4
4D
AC
13P
5D
AC
13N
63
TS_R
EF
62
CM
40DGND
24 VDRIVE
23 VSENSE
25 VSUPPLY
39 IOVDD
41 DVDD
22 IOVDD
29 DVDD
12 AVDD43 AVDD358 AVDD249 AVDD1
20 DVDD
6D
AC
14P
7D
AC
14N
8D
AC
15P
9D
AC
15N
10
DA
C1
6P11
DA
C1
6N
13AGND480AGND361AGND248AGND1
26DGND
U10
AD
AU
19
66A
WB
STZ
TP2
0
TP2
6
TP3
2TP3
3
JP1
0D
oN
otS
tuff
R1
77
0R
00
113
14
122
3
109
5
86
7
S2
JP7
PU_R
ST
[7,1
0]
DA
C1P [
4]
DA
C1N [
4]
DA
C2P [
4]
DA
C2N [
4]
DA
C3P [
4]
DA
C3N [
4]
DA
C4P [
4]
DA
C4N [
4]
TS_R
EF
DA
C5P [
4]
DA
C5N [
4]
DA
C6P [
4]
DA
C6N [
4]
DA
C7P [
4]
DA
C7N [
4]
DA
C8P [
4]
DA
C8N [
4]
DA
C9P [
5]
DA
C9N [
5]
DA
C1
0P[5
]D
AC
10N
[5]
DA
C1
1P[5
]D
AC
11N
[5]
DA
C1
2P[5
]D
AC
12N
[5]
DA
C1
3P[5
]D
AC
13N
[5]
DA
C1
4P[5
]D
AC
14N
[5]
DA
C1
5P[5
]D
AC
15N
[5]
DA
C1
6P[5
]D
AC
16N
[5]
LF [7]
MC
LKI/
XTA
LI[7
]
VD
RIV
E[2
] VS
EN
SE
[2] VSU
PPL
Y[2
]
AVD
DIO
VD
D
VSEN
SE
[2]
VSU
PPL
Y[2
]
VSEN
SE
[2]
AV
DD
PLLV
DD
PLLV
DD
XTA
LO[7
] MC
LKO
[7]
19
66
_DS
DA
TA1
[6]
19
66
_DS
DA
TA2
[6]
19
66
_DS
DA
TA3
[6]
19
66
_DS
DA
TA4
[6]
19
66
_DS
DA
TA8
[6]
19
66
_DS
DA
TA7
[6]
19
66
_DS
DA
TA6
[6]
19
66
_DS
DA
TA5
[6]19
66
_DLR
CLK
[6]19
66
_DB
CLK
[6]
CM
AV
DD
MC
LK_LF
[7]
LRC
LK_LF
[7]
VD
RIV
E [2]
19
66
_DV
DD [2]
SA
_M
OD
E[3
]
19
66
_CD
ATA
/AD
DR
1[3
] 19
66
_CO
UT/
SD
A[3
]
19
66
_CC
LK/S
CL
[3]
19
66
_CLA
TCH
/AD
DR
0[3
]
19
66
_DV
DD
[2]
Figure 59. Schematic, Page 2—ADAU196xA, PLL Loop Filter (LF) Selection and Internal Regulator
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 42 of 63
Sta
nd
alo
ne
Mo
de
sM
ast
er
SA
IS
lave
SA
I2
56
x f
s,P
LL3
84
x f
s,P
LLR
ES
ER
VE
DR
ES
ER
VE
DI2
ST
DM
TD
M4
,Pu
lse
TD
M8
,Pu
lse
TD
M1
6,
Pu
lse
TD
M8
,5
0%
Du
tyC
ycl
e
0 1 0 1 0 1 0 1
00
01
10
11
Pin
42
Pin
43
Pin
44
Pin
45
Pin
s3
2:3
1
Sta
nd
Alo
ne
Mo
de
I2C
/SP
IM
ode
Pin
42
Pin
43
Pin
44
Pin
45
Pin
42
Pin
43
Pin
44
Pin
45
I2C
Add
ress
Sele
ctio
n
Seepages5&6 forjumpers
0:B
1:A
1:A
0:B
0:B
1:A
1:A
0:B
1IN
1
2S
1A
3D
14
S1B 5VS
S6
GN
D
7S
2B
8D
29
S2A
10
IN2
11
IN3
12
S3A
13
D3
14
S3B
20
IN4
16
VD
D
17
S4B
18
D4
19
S4A
U7
AD
G7
34
_QU
AD
_S
PDT-
MU
X
113
14
122
3
109
5
86
7
S71
1314
122
3
109
5
86
7
S9
C3
50.1
0uF
C3
60.1
0uF
0:B
1:A
1:A
0:B
0:B
1:A
1:A
0:B
1IN
1
2S
1A
3D
14
S1B 5VSS
6G
ND
7S
2B
8D
29
S2A
10
IN2
11
IN3
12
S3A
13
D3
14
S3B
20
IN4
16
VD
D
17
S4B
18
D4
19
S4A
U8
AD
G7
34
_QU
AD
_S
PDT-
MU
X
15
6
42
3
S10
US
BI_
CLA
TCH
_A
[7,8
]
US
BI_
CC
LK[7
,8] U
SB
I_S
CL
[7,8
]
US
BI_
CO
UT
[7,8
] US
BI_
SD
A[7
,8]
US
BI_
CD
ATA
[7,8
]
IOV
DD
IOV
DD
IOV
DD
IOV
DD
PIN
_3
1-3
2_D
ATA
7-8
_S
EL
[6]
PIN
_31
[6] PI
N_
32[6
]
IOV
DD
AD
DR
1[3
]
AD
DR
0[3
]
AD
DR
0[3
]
AD
DR
1[3
]
I2C
/SPI
_M
OD
E[3
]
SA
_M
OD
E[2
,3]
SA
_M
OD
E[2
,3]
SA
_M
OD
E[2
,3]
I2C
/SPI
_M
OD
E[3
]
19
66
_CD
ATA
/AD
DR
1[2
]
19
66
_CO
UT/
SD
A[2
]
19
66
_CC
LK/S
CL
[2]
19
66
_CLA
TCH
/AD
DR
0[2
]
Figure 60. Schematic, Page 3—ADAU196xA Standalone Mode and I2C/SPI Option Switching
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 43 of 63
R8
0
OPE
N
R8
1
47
5R
TP6
6
TP6
7
C6
12.7
nF
R7
7
OPE
N
R7
8
47
5RTP
64
TP6
5
C6
02.7
nF
R7
1
OPE
N
R7
2
47
5R
TP6
0
TP6
1
C5
82.7
nF
R7
4
OPE
N
R7
5
47
5R
TP6
2
TP6
3
C5
92.7
nF
+
C7
51
0uF
+
C9
1
DN
P
+
C7
41
0uF
+
C9
0
DN
P
R1
28
49k
9R
127
OPE
N
R1
264
9k9
R1
25O
PEN
+
C7
71
0uF
+
C9
3
DN
P
+
C7
61
0uF
+
C9
2
DN
P
R1
32
49k
9R
131
OPE
N
R1
30
49k
9R
129
OPE
N
TP1
03 TP
102
TP1
01 TP
100
TP9
9
TP9
8
TP9
7
TP9
6
R6
9
OPE
N
R7
0
47
5R
TP5
7
TP5
8
C5
72.7
nF
+
C7
31
0uF
+
C8
9
DN
P
R1
244
9k9
R1
23O
PEN
TP9
4
TP9
3
R8
9O
PEN
R1
00O
PEN
R9
9O
PEN
R9
8O
PEN
R9
7
OPE
NR
79
0R
00
R7
60R
00
R7
30R
00
R8
80R
00
R6
80R
00
RIN
G
SLE
EVE
TIP
J12
RIN
G
SLE
EVE
TIP
J11
RIN
G
SLE
EVE
TIP
J10
RIN
G
SLE
EVE
TIP
J9
R6
6
OPE
N
R6
7
47
5R
TP5
5
TP5
6
C5
62.7
nF
+
C7
21
0uF
+
C8
8
DN
P
R1
224
9k9
R1
21O
PEN
TP9
2
TP9
1
R9
6
OPE
NR
65
0R
00
R6
3
OPE
N
R6
4
47
5R
TP5
3
TP5
4
C5
52.7
nF
+
C7
11
0uF
+
C8
7
DN
P
R1
204
9k9
R1
19O
PEN
TP9
0
TP8
9
R9
5
OPE
NR
62
0R
00
R6
0
OPE
N
R6
1
47
5R
TP5
1
TP5
2
C5
42.7
nF
+
C7
01
0uF
+
C8
6
DN
P
R1
184
9k9
R1
17O
PEN
TP8
8
TP8
7
R9
4
OPE
NR
59
0R
00
DA
C1N
[2]
DA
C1P
[2]
DA
C2N
[2]
DA
C2P
[2]
DA
C4N
[2]
DA
C4P
[2]
DA
C3N
[2]
DA
C3P
[2]
OU
T4N
OU
T4P [4
]
OU
T3N
OU
T3P [4
]
OU
T2N
OU
T2P [4]
OU
T1N
OU
T1P [4
]
DA
C5N
[2]
DA
C5P
[2]
OU
T5P
[4]
OU
T5N
OU
T8P
[4]O
UT7
P[4
]OU
T6P
[4]O
UT5
P[4
]OU
T4P
[4]O
UT3
P[4
]OU
T2P
[4]O
UT1
P[4
]D
AC
6N
[2]
DA
C6P
[2]
OU
T6P
[4]
OU
T6N
DA
C7N
[2]
DA
C7P
[2]
OU
T7P
[4]
OU
T7N
DA
C8N
[2]
DA
C8P
[2]
OU
T8P
[4]
OU
T8N
Figure 61. Schematic, Page 4—ADAU196xA DAC Output 1 to Output 8
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 44 of 63
RIN
G
SLE
EV
E
TIP
J8
RIN
G
SLE
EV
E
TIP
J7
RIN
G
SLE
EV
E
TIP
J6
RIN
G
SLE
EV
E
TIP
J5
R5
7
OPE
N
R5
8
47
5R
TP4
9
TP5
0
C5
32.7
nF
+
C6
91
0uF
+
C8
5
DN
P
R1
16
49k
9R
115
OPE
N
TP8
5
TP8
4
R9
3O
PEN
R5
60R
00
R5
4
OPE
N
R5
5
47
5R
TP4
7
TP4
8
C5
22.7
nF
+
C6
81
0uF
+
C8
4
DN
P
R1
14
49k
9R
113
OPE
N
TP8
3
TP8
2
R9
2O
PEN
R5
30R
00
R5
1
OPE
N
R5
2
47
5R
TP4
5
TP4
6
C5
12.7
nF
+
C6
71
0uF
+
C8
3
DN
P
R1
12
49k
9R
111
OPE
N
TP8
1
TP8
0
R9
1O
PEN
R5
00R
00
R4
8
OPE
N
R4
9
47
5R
TP4
3
TP4
4
C5
02.7
nF
+
C6
61
0uF
+
C8
2
DN
P
R1
10
49k
9R
109
OPE
N
TP7
9
TP7
8
R9
0O
PEN
R8
70R
00
R4
6
OPE
N
R4
7
47
5R
TP4
0
TP4
1
C4
92.7
nF
+
C8
11
0uF
+
C6
5
DN
P
R1
08
49k
9R
107
OPE
N
TP7
6
TP7
5
R8
6O
PEN
R4
50R
00
R4
3
OPE
N
R4
4
47
5R
TP3
8
TP3
9
C4
82.7
nF
+
C8
01
0uF
+
C6
4
DN
P
R1
06
49k
9R
105
OPE
N
TP7
4
TP7
3
R8
5O
PEN
R4
20R
00
R4
0
OPE
N
R4
1
47
5R
TP3
6
TP3
7
C4
72.7
nF
+
C7
91
0uF
+
C6
3
DN
P
R1
04
49k
9R
103
OPE
N
TP7
2
TP7
1
R8
4O
PEN
R3
90R
00
R3
7
OPE
N
R3
8
47
5R
TP3
4
TP3
5
C4
62.7
nF
+
C7
81
0uF
+
C6
2
DN
P
R1
02
49k
9R
101
OPE
N
TP7
0
TP6
9
R8
3O
PEN
R8
20R
00
OU
T16P
[5]O
UT1
5P[5
]OU
T14P
[5]O
UT1
3P[5
]OU
T12P
[5]O
UT1
1P[5
]OU
T10P
[5]
OU
T9P
[5]
DA
C9N
[2]
DA
C9P
[2]
OU
T9N
OU
T9P [5
]
DA
C1
0N [2]
DA
C1
0P [2]
OU
T10N
OU
T10P [5
]
DA
C1
1N [2]
DA
C1
1P [2]
OU
T11N
OU
T11P [5
]
DA
C1
2N [2]
DA
C1
2P [2]
OU
T12N
OU
T12P [5
]
DA
C1
3N [2]
DA
C1
3P [2]
OU
T13N
OU
T13P [5
]
DA
C1
4N [2]
DA
C1
4P [2]
OU
T14N
OU
T14P [5
]
DA
C1
5N [2]
DA
C1
5P [2]
OU
T15N
OU
T15P [5
]
DA
C1
6N [2]
DA
C1
6P [2]
OU
T16N
OU
T16P [5
]
Figure 62. Schematic, Page 5—ADAU196xA DAC Output 9 to Output 16
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 45 of 63
2A 1
OE
4Y
U6
SN
74LV
C1
G1
25D
RLR
C1
30.1
0uF
C2
32
7pF
C2
22
7pF
C2
12
7pF
C2
02
7pF
C1
9
27p
F
C1
8
27p
F
C1
7
27p
F
C1
6
27p
F
C1
5
27p
F
C1
4
27p
F
R2
26
1R9
R3
16
1R9
R3
06
1R9
R2
96
1R9
R2
86
1R9
R27
61R9
R26
61R9
R25
61R9
R24
61R9
C1
172
7pF
R172
61R
9
123456789
10
11
12
13
14
15
16
S3
15
642
3
S6
SPD
T_D
IP_
2SE
C_
RO
CK
ER
_TH
11
31
4
12
23
10
958
67
S5
11
31
4
12
23
10
958
67
S4
0:B
1:A
1:A
0:B
1IN
1
2S
1A
3G
ND
4S
2A
5IN
2
6D
27
S2B
8V
DD
9S
1B
10
D1
U5
C1
20.1
0uF
R2
36
1R9
84
16
_SD
ATA
[10]INTF
_D
SD
ATA
1[6
,8]
DB
CLK
_SEN
D[8
]
DLR
CLK
_SEN
D[8
]INTF
_DS
DA
TA8
[8] IN
TF_D
SD
ATA
7[8
] INTF
_DS
DA
TA6
[8] IN
TF_D
SD
ATA
5[8
] INTF
_DS
DA
TA4
[8] IN
TF_D
SD
ATA
3[8
] INTF
_DS
DA
TA2
[8]
84
16
_BC
LK[1
0]
84
16
_LR
CLK
[10]
IOV
DD
19
66
_DB
CLK
[2]
19
66
_DLR
CLK
[2]
19
66
_DS
DA
TA8
[2]
19
66
_DS
DA
TA7
[2]
19
66
_DS
DA
TA6
[2]
19
66
_DS
DA
TA5
[2]
19
66
_DS
DA
TA4
[2]
19
66
_DS
DA
TA3
[2]
19
66
_DS
DA
TA2
[2]
19
66
_DS
DA
TA1
[2]
EI3
_DB
CLK
_R
ETU
RN
[8]
EI3
_LR
CLK
_R
ETU
RN
[8]
PIN
_31
[3]
PIN
_32
[3]
PIN
_3
1-3
2_D
ATA
7-8
_SEL
[3]
IOV
DD
INTF
_D
SD
ATA
1[6
,8]
Figure 63. Schematic, Page 6—BCLK, LRCLK, and DSDATAx Switches and Routing
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 46 of 63
MC
LKso
urc
es
CLK
OU
TFe
ed
US
Bi
orA
ardv
ark
US
Bi
Inte
rfac
e
MR
lin
eco
mes
from
US
Bi
Board
Rese
t
Res
et
MC
LKS
ou
rce
Re
set
Ho
ld
Ex
tern
al
MC
LK_
IN
123456789
10
11
12
13
14
15
16
S8
TP2
31
OE
2G
ND
3 OU
TPU
T
4V
DD
U9
R3
5
10R
L2 C3
70
.10u
F
Y11
2.2
88M
Hz
R3
2
15
0RC
28
22p
F
C2
4
22p
F
R3
4
49R
9
2A 1
OE
4Y
U4
SN
74
LVC
1G
12
5DR
LR R1
4
49R
9
C9
40.1
0uF
TP1
2
1S
CL 3
SD
A 5M
ISO 7
CC
LK9
SS
2 US
B_
CLK
4 5V
00
6 BR
D_
RE
SE
T8 M
OS
I1
0 GN
D
J4H
EA
DE
R_
10W
AY_
POL_
US
BI
R1
79
3k0
1R
174
3k0
1
4 VC
C
3MR
1GN
D
2R
ES
ET
U11
AD
M8
11R
_V
2
C9
0.1
0uF
12
34
S1
R1
33
10
0k
R1
731
0k0
R3
61
0k0
R1
76
61R
9
C1
22
27p
F
JP1
D1
0
MB
R0
53
0T1G
R3
30R
00
R1
47
10k
0
R1
75
61R
9
C1
21
27p
F
MC
LKI/
XTA
LI[2
]
IOV
DD
XTA
LO [2]
MC
LKO
[2]
IOV
DD
84
16
_MC
LKI
[10]
MR [
7,9
]
US
BI_
SC
L[3
,8]
US
BI_
SD
A[3
,8]
US
BI_
CC
LK[3
,8]
US
BI_
CLA
TCH
_A
[3,8
]U
SB
I_C
DA
TA [3,8
]
IOV
DD
PU_
RS
T[2
,10]
MR
[7,9
]
IOV
DD
EI3
_MC
LKI
[8]
OM
CK
_FE
ED[1
0]
US
BI_
CO
UT
[3,8
]U
SB
I_5V
00 [8
]
EI3
_MC
LKO [8
]
OS
C_
EN
B[7
]O
SC
_EN
B [7]
EI3
_IO
VD
D
MC
LK_S
EL [8]
MC
LK_
LF[2
]LRC
LK_
LF[2
]LF
[2]
IOV
DD
Figure 64. Schematic, Page 7—MCLK Selection, USBi Interface, CLKOUT Feed, and Reset Generator
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 47 of 63
Ex
tern
al
MC
LK_
IN
Ex
tern
al
BC
LKIN
Exte
rna
lLR
CLK
IN
Inst
all
1k
50
oh
mre
sist
or
for
R1
46
toe
na
ble
con
tro
lo
fth
eS
PI
po
rtv
iath
eU
SB
i.
LRC
LKO
ut
BC
LKO
ut
DIR
EC
TIO
NP
IN:
H=
A->
BL=
A<
-B
DIR
EC
TIO
NP
IN:
H=
A->
BL=
A<
-B
DIR
EC
TIO
NP
IN:
H=
A->
BL=
A<
-B
DIR
EC
TIO
NP
IN:
H=
A->
BL=
A<
-B
DIR
EC
TIO
NP
IN:
H=
A->
BL=
A<
-B
1V
CC
A2
DIR
3A
14
A2
5A
36
A4
7A
58
A6
9A
71
0A
81
1G
ND
12
GN
D1
3G
ND
14
B8
15
B7
16
B6
17
B5
18
B4
19
B3
20
B2
21
B1
22
OE
23
VC
CB
24
VC
CB
U2
0
SN
74LV
CH
8T2
45D
BR
_8B
ITLV
LSH
FT
R1
35
49R
9
R1
36
49R
9
R1
691
0k0
R1
71
10k
0
2S
CLA
3S
DA
A7
SC
LB6
SD
AB
1V
CC
A8
VC
CB
4G
ND
5E
NU
12
PCA
95
17D
P-T_
I2C
BU
SR
PT_
LVLT
RA
NS
_TS
SO
P8
1
VC
CA
21D
IR3
2D
IR
41A
15
1A
26
2A
17
2A
2
8G
ND
19
GN
D2
10
2B
2
11
2B
1
12
1B
2
13
1B
1
14
2O
E
15
1O
E
16
VC
CB
U18
SN
74A
VC
4T2
45P
WR
_4B
IT_TR
AN
SC
VR
R1
54
10k
0
1
VC
CA
21D
IR3
2D
IR
41A
15
1A
26
2A
17
2A
2
8G
ND
19
GN
D2
10
2B
2
11
2B
1
12
1B
2
13
1B
1
14
2O
E
15
1O
E
16
VC
CB
U17
SN
74A
VC
4T2
45P
WR
_4B
IT_TR
AN
SC
VR
R1
53
10k
0
R1
62
OPE
N R1
63
3k3
2
R1
451
0k0
1 2 3 4 5 6 7 891
01
11
21
31
41
51
6
R1
70
10R
0
C1
15
0.1
0uF
C1
13
0.1
0uF
C1
07
0.1
0uF
C1
09
0.1
0uF
C9
8
0.1
0uF
C97
0.1
0uF
C1
05
0.1
0uF
C1
06
0.1
0uF
C1
01
0.1
0uF
C1
00
0.1
0uF
2A 1
OE
4Y
U1
5
C104
0.10uF
C103
0.10uF
2A
4Y
1
OEU1
4
SN
74LV
C1
G1
26D
RLR
R1
594
9R9
R1
644
9R9
R1
664
9R9
R1
49
49R
9
R1
614
9R9
R1
674
9R9
TP13T
P14
R1
433
3R2
R1
423
3R2
1 3 5 7 9
2 4 6 81
01
11
31
5
12
14
16
J3H
EA
DER
_1
6WA
Y_U
NS
HR
OU
D
JP4
JP2
JP3
1
VC
CA
21D
IR3
2D
IR
41A
15
1A
26
2A
17
2A
2
8G
ND
19
GN
D2
10
2B
2
11
2B
1
12
1B
2
13
1B
1
14
2O
E
15
1O
E
16
VC
CB
U13
SN
74A
VC
4T2
45P
WR
_4B
IT_TR
AN
SC
VR
R1
581
0R
R1
651
0RR
160
10R
R1
50
33R
2
R1
48
33R
2
R1
52
33R
2
R1
403
3R2
R1
413
3R2
R1
38
33R
2
R1
39
33R
2
1 2 3 4 5 6 7 891
01
11
21
31
41
51
6
R1
68
10R
0
JP11JP12
32
A4
2Y
U1
-B
74
HC
04
D-T
1
VC
CA
21D
IR3
2D
IR
41A
15
1A
26
2A
17
2A
2
8G
ND
19
GN
D2
10
2B
2
11
2B
1
12
1B
2
13
1B
1
14
2O
E
15
1O
E
16
VC
CB
U21
SN
74A
VC
4T2
45P
WR
_4B
IT_TR
AN
SC
VR
C1
35
0.1
0uF
C1
36
0.1
0uF
R4
10k
0R
137
10k
0
US
BI_
SC
L[3
,7]
US
BI_
CO
UT
[3,7
]
US
BI_
SD
A[3
,7]
EI3
_IO
VD
DIO
VD
D
EI3
_DS
DA
TA1
[8,9
]EI3
_DS
DA
TA2
[8,9
]EI3
_DS
DA
TA3
[8,9
]EI3
_DS
DA
TA4
[8,9
]EI3
_DS
DA
TA5
[8,9
]EI3
_DS
DA
TA6
[8,9
]EI3
_DS
DA
TA7
[8,9
]EI3
_DS
DA
TA8
[8,9
]
EI3
_IO
VD
DIO
VD
D
EI3
_SC
L[9
]EI3
_SD
A[9
]
EI3
_IO
VD
DIO
VD
D
IOV
DD
EI3
_IO
VD
D
US
BI_
5V00
[7]
DLR
CLK
_SEN
D[6
]
DB
CLK
_SEN
D[6
]
IOV
DD
EI3
_IO
VD
D
EI3
_DLR
CLK
0[9
]
EI3
_DB
CLK
0[9
]
EI3
_DB
CLK
1[9
]
EI3
_DLR
CLK
1[9
]
INTF
_D
SD
ATA
8[6
]IN
TF_D
SD
ATA
7[6
]IN
TF_D
SD
ATA
6[6
]IN
TF_D
SD
ATA
5[6
]IN
TF_D
SD
ATA
4[6
]IN
TF_D
SD
ATA
3[6
]IN
TF_D
SD
ATA
2[6
]IN
TF_D
SD
ATA
1[6
]
EI3
_MC
LK[8
,9]
EI3
_MC
LKI
[7]
EI3
_MC
LK[8
,9] M
CLK
_SE
L[7
,8]
MC
LK_S
EL
[7,8
]
EI3
_IO
VD
D
EI3
_IO
VD
D
EI3
_CCLK
[9]
US
BI_
CCLK
[3,7
]
EI3
_CD
ATA
[9]
EI3
_CLA
TCH
_A
[9]
EI3
_CLA
TCH
_B
[9]
EI3
_CLA
TCH
_C
[9]
US
BI_
CLA
TCH
_A
[3,7
]
US
BI_
CD
ATA
[3,7
]
EI3
_MC
LKO
[7]
EI3
_CO
UT
[9]
US
BI_
CLA
TCH
_B
US
BI_
CLA
TCH
_C
EI3
_D
BC
LK_R
ETU
RN
[6]
EI3
_LR
CLK
_R
ETU
RN
[6]
EI3
_D
SD
ATA
1[8
,9]
EI3
_D
SD
ATA
2[8
,9]
EI3
_D
SD
ATA
3[8
,9]
EI3
_D
SD
ATA
4[8
,9]
EI3
_D
SD
ATA
5[8
,9]
EI3
_D
SD
ATA
6[8
,9]
EI3
_D
SD
ATA
7[8
,9]
EI3
_D
SD
ATA
8[8
,9]
IOV
DD
_S
WIT
CH
OV
ER
[9,1
1]
EI3
_IO
VD
DIO
VD
D
Figure 65. Schematic, Page 8—Level Shifters and Master Clock Direction Control
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 48 of 63
EI3
1A
EI3
1B
SP
OR
T1
_D
0S
PO
RT
1_
D1
SP
OR
T1
_C
LK
SP
OR
T1
_F
SS
PO
RT
0_
D1
SP
OR
T0
_D
0S
PO
RT
0_
FS
SP
OR
T0
_C
LK
SP
OR
T3
_D
0S
PO
RT
3_
D1
SP
OR
T3
_C
LK
SP
OR
T3
_F
SS
PO
RT
2_
D1
SP
OR
T2
_D
0S
PO
RT
2_
FS
SP
OR
T2
_C
LK
SP
I0_
SE
L_A
SP
I0_
MIS
OS
PI0
_M
OS
I
SP
I0_
CLK
SD
A0
'S
CL0
'
SD
A0
'S
CL0
'
RE
SE
T_
OU
T'
RE
SE
T_
OU
T'
DA
U_
MC
LK
SP
I0_
SE
L_B
SP
I0_
SE
L_C
R1
46
isu
sed
tose
nd
po
we
rto
the
ma
inb
oa
rdR
13
isu
sed
tore
ceiv
ep
ow
er
fro
mth
em
ain
bo
ard
R1
46
OPE
N1 2 3 4 5 6 7 8 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J1
HIR
OS
E_FX
8-1
20S
-SV(2
1)_S
OC
KET
1 2 3 4 5 6 7 8 910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J2
HIR
OS
E_FX
8-1
20S
-SV(2
1)_S
OC
KET
R1
3O
PEN
D9
Sch
ottk
y
R1
34
49R
9
+C
102
47u
F
EI3
_IO
VD
D5V
0D
D
EI3
_IO
VD
D
EI3
_SC
L [8]
EI3
_SD
A [8]
EI3
_DS
DA
TA1
[8]
EI3
_DS
DA
TA2
[8]
EI3
_DS
DA
TA3
[8]
EI3
_DS
DA
TA4
[8]
EI3
_DS
DA
TA5
[8]
EI3
_DS
DA
TA6
[8]
EI3
_DS
DA
TA7
[8]
EI3
_DS
DA
TA8
[8]
EI3
_CLA
TCH
_A[
8]
EI3
_CD
ATA
[8]
EI3
_CCLK
[8]
EI3
_CO
UT
[8]
MR
[7]
EI3
_DLR
CLK
0[8
]
EI3
_DB
CLK
0[8
]
EI3
_DLR
CLK
1[8
]
EI3
_DB
CLK
1[8
]
EI3
_MC
LK[8
]
EI3
_CLA
TCH
_B
[8] EI3
_CLA
TCH
_C
[8]
IOV
DD
_S
WIT
CH
OV
ER
[8,1
1] SD
P_PO
WER
[11]
Figure 66. Schematic, Page 9—SDP Interface Connectors
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 49 of 63
Error
Hig
h
Nor
m
On
Off
RER
R
NV
ER
R
ER
RO
RS
EM
PHPH
DET
RA
TE
ValidAudio
>88kHz
MA
STE
R
SLA
VE
SER
IAL
POR
TC
ontr
ol
12
8xFs
25
6xFs RM
CK
Freq
|---
----
-S
ER
IAL
POR
TFo
rmat
----
---|
SFS
EL
[1:0
]0
0=
LJ2
4bit
01
=I2
S2
4bit
10
=R
J2
4bit
11
=D
irec
tA
ES
1 0
1 0
SFS
EL1
SFS
EL0
C7 1
0nF
C6 1
0nF
C3
0.1
0uF C5
0.1
0uF
L46
00
Oh
m@
10
0M
Hz
D3
RedDiffusedR5
39
2R
D2
GreenDiffusedR2
39
2R
L1 60
0O
hm
@1
00
MH
z
C1
330.1
0uF
11A2 1Y U1
-A
53A6 3Y U1
-C
4R
XP0
5R
XN
8FI
LT6 VA
23 V
D
26
SD
OU
T2
8O
LRC
K2
7O
SC
LK2
4R
MC
K
10
RX
SE
L11
1R
XS
EL0
12
TXS
EL1
13
TXS
EL0
19
C1
8U
17
RC
BL
14
NV
/RE
RR
15
AU
DIO
3R
XP1
2R
XP2
1R
XP3
20
TX
16
96
KH
Z
21 V
L
9R
ST
25
OM
CK
7
AG
ND
22
DG
ND
U3
CS
84
16
_SPD
IF_
RX
C1
22n
F
C2
1.0
nF
R7
3k0
1
C4
0.1
0uF
R1
444
7k5
94A8 4Y U1
-D
115A10 5Y U1
-E
136A12 6Y U1
-F
74
HC
04
D-TD1
YellowDiffusedR1
39
2R
R8
61R
9R
11
61R
9R
12
61R
9R
96
1R9
+
C8
10u
F
Def
ault
RS
6
47k
5
Def
ault
RS
5
47k
5
5N
C
4N
C1
OU
T
2GN
D
3 DV
DD
U2
PLR
13
5/T1
0_S
PDIF
_R
X_LO
WPR
O
L3 60
0O
hm
@1
00
MH
z
C9
90.1
0uF
R6
0R
00
R1
0O
PEN
R3
10k
0
Def
ault
RS
2
47k
5
Def
ault
RS
4
47k
5
Def
ault
RS
1
47k
5
Def
ault
RS
3
47k
5
Def
ault
RS
7
47k
5
TP2
IOV
DD
84
16
_SD
ATA
[6]
84
16
_LR
CLK
[6]
84
16
_BC
LK[6
]8
41
6_M
CLK
I[7
]
IOV
DD
3V
3D
D
PU_R
ST
[2,7
]
IOV
DD
IOV
DD
IOV
DD
3V
3D
D
OM
CK
_FE
ED [7]
Figure 67. Schematic, Page 10—S/PDIF Receiver
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 50 of 63
3v3
Lin
ear
Su
ppl
y
+6
VD
CM
AX
GN
D
Plan
ede
cou
plin
g
Loca
lPow
er
for
Level
Matc
hin
gIn
terf
ace
D8
7.0
V
TP9
5
TP2
4
L5
60
0O
hm
@1
00
MH
z
C3
10.1
0uF
+C
114
47u
F
TP8
R1
54
75R
D4 Gre
enD
iffu
sed
R1
64
75R
D5
GreenDiffused
TP8
6TP5
9TP1
0TP
7TP
27T
P104T
P105T
P68
TP1
TP6
TP1
1TP7
7TP1
06T
P42
2 13
J13
D7
1N
58
19H
W-7
-F
R1
9
0R
00
C9
50.1
0uF
C1
34
0.1
0uF
C9
60.1
0uF
C1
18
0.1
0uF
TP1
5
TP9
TP2
8TP1
9TP1
07T
P16
R1
7
0R
00
1V
OU
T
2V
OU
T
3GND
4S
EL1
5S
EL0
6EN
7V
IN
8V
IN
9EPU16
AD
P198
R1
55
0R
00
JP6
JP5D
61N
58
19H
W-7
-F
R1
511
0k0
3IN
2O
UT
1GND
4O
UT
U2
3A
DP3
33
8-3
.3V
C1
39
1.0
uF
C1
40
1.0
uF
5V
0D
D
3V
3D
D5V
0D
D
IOV
DD
AV
DD
EI3
_IO
VD
D3V
3D
D
IOV
DD
_S
WIT
CH
OV
ER
[8,9
]
SD
P_PO
WE
R[9
]
Figure 68. Schematic, Page 11—Power Supply
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 51 of 63
Figure 69. Top Assembly
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 52 of 63
Figure 70. Top Layer Copper
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 53 of 63
Figure 71. L2 Ground
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 54 of 63
Figure 72. L3 Power
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 55 of 63
Figure 73. Bottom Copper
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 56 of 63
Figure 74. Bottom Assembly
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 57 of 63
BILL OF MATERIALS—REVISION B PCB Table 4. Qty Reference Description Manufacturer Part Number Vendor Vendor Order No. 1 U6 Multibit Σ-Δ DAC Analog Devices ADAU1962AWBSTZ or
ADAU1966AWBSTZ Analog Devices ADAU1962AWBSTZ or
ADAU1966AWBSTZ 1 J12 10-way shroud,
polarized header 3M N2510-6002RB Digi-Key MHC10K-ND
1 U5 12.288 MHz, fixed SMD oscillator, 3.3 V to 5 V dc
Cardinal Components
CPPFX C 7 L T-A7 BR-12.288MHz TS
Cardinal Components
CPPFX C 7 L T-A7 BR-12.288MHz TS
2 J6, J8 120-pin socket, 0.6 mm
Hirose Electric FX8-120S-SV(21) Digi-Key H1219-ND
1 U1 15 Mbps fiber optic receiving module with shutter
Toshiba TORX147L(FT) Digi-Key TORX147LFT-ND
1 U2 192 kHz digital receiver, 28-TSSOP
Cirrus Logic CS8416-CZZ Digi-Key 598-1124-5-ND
10 JP1, JP3 to JP9, JP11, JP21
2-pin header, unshrouded, jumper, 0.10"; use Tyco 881545-2 shunt
Sullins Electronics Corp
PBC02SAAN or cut down PBC36SAAN
Digi-Key S1011E-02-ND
1 U8 200 kHz, 1 A, buck regulator
Analog Devices ADP3050ARZ Digi-Key ADP3050ARZ-R7CT-ND
1 J11 28-way, unshrouded
3M PBC14DAAN, or cut down PBC36DAAN
Digi-Key S2011E-14-ND
1 U9 3-term adj voltage regulator DPAK
ST Microelectronics
LM317MDT-TR Digi-Key 497-1574-1-ND
11 JP2, JP10, JP12 to JP20 3-pos SIP header Sullins PBC03SAAN or cut down PBC36SAAN
Digi-Key S1011E-03-ND
1 JP22 3-pos T-header Sullins PBC03SAAN or cut down PBC36SAAN
Digi-Key S1011E-03-ND plus single pin
1 J5 8-way, unshrouded, header dual row
Sullins Electronics Corp
PBC04DAAN or cut down PBC36DAAN
Digi-Key S2011E-04-ND or cut down S2011E-36-ND
27 C9 to C10, C14, C16, C22, C32, C39,C49, C55, C62, C74, C80, C83, C89, C91, C93, C95, C11, C125 to C131, C133 to C134
Alum electrolytic capacitor, FC 105°, SMD_B, 10 μF
Panasonic EC EEE-FC1C100R Digi-Key PCE3995CT-ND
4 C107, C118 to C119, C132
Alum electrolytic capacitor, FC 105°, 47 μF, SMD_D
Panasonic EC EEE-FC1C470P Digi-Key PCE4000CT-ND
3 U4, U14, U18 Buffer 3-state, single gate
Texas Instruments SN74LVC1G125DRLR Digi-Key 296-18012-1-ND
1 Y1 Crystal, 12.288 MHz, SMT, 18 pF
Abracon Corp ABM3B-12.288MHZ-10-1-U-T Digi-Key 300-8198-1-ND
4 L1, L3 to L4, L7 Chip ferrite bead, 600 Ω at 100 MHz
TDK Corp MMZ1005S601C Digi-Key 445-2162-1-ND
2 L2, L5 Chip ferrite bead, 600 Ω at 100 MHz
Steward HZ0805E601R-10 Digi-Key 240-2399-1-ND
3 R1 to R3 Chip resistor, 1%, 100 mW, thick film, 0603, 392R
Rohm MCR03EZPFX3920 Digi-Key RHM392HCT-ND
1 R5 Chip resistor, 1%, 100 mW thick film, 0603, 75R0
Panasonic EC ERJ-3EKF75R0V Digi-Key P75.0HCT-ND
2 R13, R18 Chip resistor, 1%, 475R, 125 mW, thick film, 0603
Panasonic EC ERJ-3EKF4750V Digi-Key P475HCT-ND
7 RS1 to RS7 Chip resistor, 1%, 47k5, 125 mW,
Panasonic EC ERJ-3EKF4752V Digi-Key P47.5KHCT-ND
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 58 of 63
Qty Reference Description Manufacturer Part Number Vendor Vendor Order No. thick film, 0603
1 R126 Chip resistor, 100k, 1%, 63 mW, thick film, 0402
Rohm MCR01MZPF1003 Digi-Key RHM100KLCT-ND
14 R4, R9, R20, R46, R127, R130, R134, R137 to R140, R144, R149, R157
Chip resistor, 1%, 10k0, 63 mW, thick film, 0402
Rohm MCR01MZPF1002 Digi-Key RHM10.0KLCT-ND
1 R121 Chip resistor, 1%, 10k2, 63 mW, thick film, 0402
Vishay/Dale CRCW040210K2FKED Digi-Key 541-10.2KLCT-ND
5 R10 to R12, R21, R49 Chip resistor, 1%, 150 R, 63 mW, thick film, 0402
Rohm MCR01MZPF1500 Digi-Key RHM150LCT-ND
1 R120 Chip resistor, 1%, 1k15, 63 mW, thick film, 0402
Panasonic EC ERJ-2RKF1151X Digi-Key P1.15KLCT-ND
2 R56, R146 Chip resistor, 1%, 1k50, 63 mW, thick film, 0402
Panasonic EC ERJ-2RKF1501X Digi-Key P1.50KLCT-ND
1 R50 Chip resistor, 1%, 1M00, 63 mW, thick film, 0402
Rohm MCR01MZPF1004 Digi-Key RHM1.00MLCT-ND
1 R124 Chip resistor, 1%, 243R, 63 mW, thick film, 0402
Vishay/Dale CRCW0402243RFKED Digi-Key 541-243LCT-ND
1 R122 Chip resistor, 1%, 32k4, 63 mW, thick film, 0402
Vishay/Dale CRCW040232K4FKED Digi-Key 541-32.4KLCT-ND
5 R59, R62 to R63, R66, R141
Chip resistor, 1%, 33R2, 63 mW, thick film, 0402
Panasonic EC ERJ-2RKF33R2X Digi-Key P33.2LCT-ND
3 R6, R111, R155 Chip resistor, 1%, 3K01, 63 mW, thick film, 0402
Rohm MCR01MZPF3011 Digi-Key RHM3.01KLCT-ND
2 R25, R145 Chip resistor, 1%, 3k32, 63 mW, thick film, 0402
Vishay/Dale CRCW04023K32FKED Digi-Key 541-3.32KLCT-ND
1 R123 Chip resistor, 1%, 402R, 63 mW, thick film, 0402
Vishay/Dale CRCW0402402RFKED Digi-Key 541-402LCT-ND
16 R31, R33, R35, R37, R44, R51, R57, R64, R70, R76, R82, R88, R91, R93, R95, R97
Chip resistor, 1%, 475R, 63 mW, thick film, 0402
Stackpole RMCF0402FT475R Digi-Key RMCF0402FT475RCT-ND
1 R125 Chip resistor, 1%, 47k5, 63 mW, thick film, 0402
Rohm MCR01MZPF4752 Digi-Key RHM47.5KLCT-ND
16 R8, R22, R26, R29, R45, R52, R58, R65, R71, R77, R83, R89, R100, R102 R104, R106
Chip resistor, 1%, 49k9, 63 mW, thick film, 0402
Vishay/Dale CRCW040249K9FKED Digi-Key 541-49.9KLCT-ND
15 R24, R38, R42, R53, R128 to R129, R131 to R132, R142 to R143, R147 to R148, R150 to R152
Chip resistor, 1%, 49R9, 63 mW, thick film, 0402
Rohm MCR01MZPF49R9 Digi-Key RHM49.9LCT-ND
1 R27 Chip resistor, 1%, 562R, 63 mW, thick film, 0402
Vishay/Dale CRCW0402562RFKED Digi-Key 541-562LCT-ND
8 R67, R72 to R73, R78 to R79, R84 to R85, R90
Chip resistor, 1%, 68R1, 63 mW, thick film, 0402
Rohm MCR01MZPF68R1 Digi-Key RHM68.1LCT-ND
18 R39, R43, R107, R117 to Chip resistor, 5%, Panasonic ECG ERJ-2GE0R00X Digi-Key P0.0JCT-ND
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 59 of 63
Qty Reference Description Manufacturer Part Number Vendor Vendor Order No. R119, R158 to R161, R170 to R177
0R00, 100 mW, thick film, 0402
2 R14 to R15 Chip resistor, 5%, 0R00, 125 mW, thick film, 0805
Panasonic EC ERJ-6GEY0R00V Digi-Key P0.0ACT-ND
1 S1 DPDT slide switch vertical
E-Switch EG2207 Digi-Key EG1940-ND
48 R7, R19, R23, R28, R30, R32, R34, R36, R40 to R41, R47, to R48, R54 to R55, R60 to R61, R68 to R69, R74 to R75, R80 to R81, R86 to R87, R92, R94, R96, R98 to R99, R101, R103, R105, R108 to R110, R112 to R116, R162 to R169
Open Open
2 R133, R156 Open Open 32 TP7, TP10 to TP12,
TP16, TP18 to TP19, TP22, TP24, TP37, TP40, TP42, TP47, TP49, TP52, TP55, TP65, TP68, TP70, TP73, TP75, TP77, TP87, TP89 to TP91, TP93, TP97 to TP101
Open Open
3 D3, D5 to D6 Green diffused, 10 millicandela, 565 nm 1206
Lumex Opto SML-LX1206GW-TR Digi-Key 67-1002-1-ND
1 U11 IC 2-bit, dual bus, TXRX 8-SSOP
Texas Instruments SN74LVC2T45DCTR DigiKey 296-16845-1-ND
3 U13, U16 to U17 IC 8-bit, dual bus, TXRX 24-SSOP
Texas Instruments SN74LVCH8T245DBR DigiKey 296-21067-1-ND
1 U15 IC I2C bus, repeater 8-TSSOP
NXP Semiconductor
PCA9517DP-T DigiKey 568-1829-2-ND
1 U3 IC inverter, hex TTL/LSTTL 14 SOIC
NXP Semiconductor
74HC04D-T DigiKey 568-1384-1-ND
1 J13 Mini power jack, 0.08" R/A TH
Switchcraft, Inc. RAPC722X Digi-Key SC1313-ND
32 TP1 to TP6, TP8 to TP9, TP13 to TP15, TP17, TP20 to TP21, TP23, TP25, TP27, TP36, TP38, TP44 to TP45, TP56, TP60, TP71, TP86, TP88, TP92, TP94, TP102, TP104 to TP106
Mini test point, white, 0.1" OD
Keystone Electronics
5002 Digi-Key 5002K-ND
2 C113 to C114 Multilayer ceramic, 47 μF, 10 V, X5R, 1206
Kemet C1206C476M8PACTU Digi-Key 399-5508-6-ND
44 C1, C4, C7, C11 to C12, C27, C33, C36 to C37, C40 to C42, C44, C47, C53, C65, C67 to C68, C71, C75, C77, C105, C108, C110 to C112, C116 to C117, C120 to C123, C135 to C140, C142 to C143, C145 to C146, C152, C154
Multilayer ceramic, 0.10 μF, 16 V, X7R, 0402
Murata ENA GRM155R71C104KA88D Digi-Key 490-3261-1-ND
5 C43, C45, C72, C76, C109
Multilayer ceramic, 47 μF, 16 V, X7R, 0603
Taiyo Yuden EMK107B7474KA-T Digi-Key 587-1250-1-ND
2 C5 to C6 Multilayer ceramic, TDK Corp C1608C0G1E103J Digi-Key 445-2664-1-ND
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 60 of 63
Qty Reference Description Manufacturer Part Number Vendor Vendor Order No. 10 nF, 25 V, NP0, 0603
1 C20 Multilayer ceramic, 5.6 nF, 25 V, NP0, 0603
TDK Corp C1608C0G1E562J Digi-Key 445-2666-1-ND
1 C2 Multilayer ceramic, 22 nF, 25 V, NP0, 0805
Murata ENA GRM21B5C1H223JA01L Digi-Key 490-1644-1-ND
2 C28, C124 Multilayer ceramic, 10 pF, 50 V, NP0, 0402
Kemet C0402C100J5GACTU Digi-Key 399-1011-1-ND
3 C50, C52, C141 Multilayer ceramic, 2.2 pF, 50 V, NP0, 0402
Johanson Technology
500R07S2R2BV4T Digi-Key 712-1279-1-ND
2 C29, C34 Multilayer ceramic, 22 pF, 50 V, NP0, 0402
Murata ENC GRM1555C1H220JZ01D Digi-Key 490-1283-1-ND
2 C17, C104 Multilayer ceramic, 390 pF, 50 V, NP0, 0402
Murata ENA GRM1555C1H391JA01D Digi-Key 490-1296-1-ND
8 C56 to C58, C60, C63 to C64, C66, C70
Multilayer ceramic, 4.7 pF, 50 V, NP0, 0402
Johanson Technology
500R07S4R7BV4T Digi-Key 12-1166-1-ND
1 C18 Multilayer ceramic, 2.2 nF, 50 V, NP0, 0603
Murata Electronics GRM1885C1H222JA01D Digi-Key 490-1459-1-ND
1 C3 Multilayer ceramic, 1.0 nF, 50 V, NP0, 0603
Panasonic EC ECJ-1VC1H102J Digi-Key PCC2151CT-ND
16 C23 to C-26, C31, C38, C48, C54, C61, C73, C79, C82, C84 to C87
Multilayer ceramic, 2.7 nF, 50 V, NP0, 0603
Murata ENA GRM1885C1H272JA01D Mouser 81-GRM185C1H272JA01D
1 C106 Multilayer ceramic, 68 nF, 50 V, NP0, 1206
Murata GCM31C5C1H683JA16L Digi-Key 490-5323-1-ND
1 C21 Multilayer ceramic, 39 nF, 50 V, X7R, 0805
Panasonic EC ECJ-2VB1H393K Digi-Key PCC1835CT-ND
16 C8, C13, C15, C19, C30, C35, C46, C51, C59, C69, C78, C81, C88, C90, C92, C94
10 μF, not fitted Panasonic EC EEE-FC1C100R Digi-Key PCE3995CT-ND
1 JP23 2 jumper, not fitted
Sullins Electronics Corp
PBC02SAAN or cut down PBC36SAAN
Digi-Key S1011E-02-ND
1 Q1 PNP transistor Zetex, Inc. ZX5T953GTA Digi-Key ZX5T953GCT-ND 1 J1 RCA jack, PCB TH
mount, R/A yellow Connect-Tech Products Corp.
CTP-021A-S-YEL Connect-Tech CTP-021A-S-YEL
1 D4 Red diffused, 6.0 millicandela, 635 nm 1206
Lumex Opto SML-LX1206IW-TR Digi-Key 67-1003-1-ND
2 R135 to R136 Resistor network, isolated 8 res, 33R0
CTS Corp. 741X163330JP Digi-Key 741X163330JPCT-ND
2 J2, J4 SMA receptacle, straight PCB mount
Amp-RF Division 901-144-8RFX Digi-Key ARFX1231-ND
1 L6 SMT power inductor, 22 μH
Coilcraft MSS12778-223MLB Coilcraft MSS12778-223MLB
1 U12 Sngl bus, buff gate, 3ST SOP-5
Texas Instruments SN74LVC1G126DRLR DigiKey 296-18013-1-ND
1 D8 Schottky 30 V, 0.2 A, SOD123 diode
On Semiconductor BAT54T1G Digi-Key BAT54T1GOSCT-ND
2 D9 to D10 Schottky 30 V, 0.5 A, SOD123 diode
On Semiconductor MBR0530T1G Digi-Key MBR0530T1GOSCT-ND
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 61 of 63
Qty Reference Description Manufacturer Part Number Vendor Vendor Order No. 1 D7 Schottky 40 V, 1 A,
SOD123 diode Diodes, Inc 1N5819HW-7-F Digi-Key 1N5819HW-FDICT-ND
8 J3, J9 to J10, J14 to J18 Sterero mini jack SMT
CUI, Inc. SJ-3523-SMT Digi-Key CP-3523SJCT-ND
1 D1 TVS Zener 15 V, 600 W SMB
ON Semiconductor 1SMB15AT3G Digi-Key 1SMB15AT3GOSCT-ND
1 S2 Tact switch, 6 mm, gull wing, SPST-NO
Tyco/Alcoswitch FSM6JSMA Digi-Key 450-1133-ND
1 D2 Yellow diffused, 4.0 millicandela, 585 nm 1206
CML Innovative Tech
CMD15-21VYD/TR8 Digi-Key L62307CT-ND
1 U10 Microprocessor voltage supervisor, logic low RESET output
Analog Devices ADM811RARTZ-REEL7 Analog Devices ADM811RARTZ-REEL7
UG-564 EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide
Rev. A | Page 62 of 63
NOTES
I2C refers to a communications protocol developed by Philips Semiconductors (now NXP Semiconductors).
EVAL-ADAU1962AZ/EVAL-ADAU1966AZ User Guide UG-564
Rev. A | Page 63 of 63
ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
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