ELCT501 Digital System Design Winter 2012 Tutorial #8 FPGA ... · Digital System Design Winter 2012...

ELCT501 Digital System Design

Winter 2012

Tutorial #8FPGA Complete Design Flow Example

Dr M. Abd El Ghany

Eng. Salma Hesham

Faculty of IETELCT501 Tutorial #7 winter 2012

Dr M. Abd El Ghany

Eng. Salma Hesham

Design a 4-bit Up-Counter with Enable

EReset

Count4

Up-Counter

Design Flow Steps:1. Write VHDL code for the counter.2. Test the counter using behavioral simulation.3. Synthesize the design.4. Assign inputs and outputs locations on the FPGA5. Implement the design.

Dr M. Abd El Ghany

Eng. Salma Hesham

1. Write the VHDL Code for the Up-Counter

EReset

Count4

Up-Counter

Dr M. Abd El Ghany

Eng. Salma Hesham

EReset

Count4

Up-Counter

Dr M. Abd El Ghany

Eng. Salma Hesham

EReset

Count4

Up-Counter

Dr M. Abd El Ghany

Eng. Salma Hesham

2. Write Test Bench for the up-Counter

EReset

Count4

Up-Counter

Dr M. Abd El Ghany

Eng. Salma Hesham

2. Test The Design using Behavioral Simulation

When the Enable E=‘0’ the counter is disabledand the count is kept

constant till E=‘1’ again

Dr M. Abd El Ghany

Eng. Salma Hesham

3. Synthesize the Design

Dr M. Abd El Ghany

Eng. Salma Hesham

4. Assign inputs and Outputs Locations on Board

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

Enter locations of each input and output on

the FPGA Board

Dr M. Abd El Ghany

Eng. Salma Hesham

Enter locations of each input and output on the

FPGA Board

Dr M. Abd El Ghany

Eng. Salma Hesham

5. Configure The FPGA Board

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

Dr M. Abd El Ghany

Eng. Salma Hesham

ELCT501 Digital System Design Winter 2012 Tutorial #8 FPGA ... · Digital System Design Winter 2012...

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