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ELCT 501:
Digital System Design
Lecture 1: Introduction
Dr. Mohamed Abd El Ghany,
Department of Electronics and Electrical Engineering
Mohamed.abdel-ghany@guc.edu.eg
Administrative Rules
Course components:
Lecture: Thursday (fourth slot), 13:15-14:45 (H8)
Office Hours: Thursday after lecture
Teaching assistant: Eng. Salma Hesham
Grading:
Assignments: 10% (2 x 5%)
Quizzes: 10% (2x 5%)
Project : 10%
Mid term exam: 30%
Final exam: 40%
2 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Administrative Rules
Quizzes:
Quiz 1: Thursday, 4/10/2012, 13:15 (H8)
Quiz 2: Thursday,
Quiz 3: Thursday,
Project:
Announcement : Thursday,
Due date:
3 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Course Policies
Take notes during the lectures, Don’t expect that everything said during the lecture will be documented in the slides
I expect that anything “said” during a lecture or tutorials will be known by all students. So, if you don’t attend, then please “at least” ask!
It is your responsibility to check the course website regularly for any announcements or material
4 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Course Objective
Understanding the basic low-level background of digital
circuits
Recognizing the different types of memories and
programmable logic devices
Analysis and Design of Advanced Combinational and
Sequential Circuits
Applying a complete design flow targeting FPGA platforms
Applying the concept of pipelining to boost the throughput
of a digital system
Analysis and Design of Efficient Arithmetic Circuits
5 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Text and Reference Books
John Wakerly, “Digital Design,” Prentice Hall, ISBN:
0-13-176059-9
Neil Storey, “Electronics- A System Approach,”
Prentice Hall, ISBN 0-13-129396-6
Stephen Brown, and Zvonko Vranesic,
“Fundamentals of Digital Logic with VHDL Design,”
Mc Graw Hill, ISBN 007-124482-4
Ercegovac and Lang, “Digital Arithmetic,”
6 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Prerequisites
Digital Logic Design
Electric Circuits I, II
Introduction to Computer
Programming
7 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
What is inside your electronic
devices?
8 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
The design
process of a
typical IC is
presented by
this course.
ELCT 501: Digital System
Design
Winter 2011
Integrated Circuits (ICs)
9 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Analog Digital Mixed
Op-amps
LNA
Oscillator
microprocessor
DSPs
ADC
DAC
ELCT 501: Digital System
Design
Winter 2011
Digital Integrated Circuits (DICs)
10 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Bipolar FET(MOS)
DICs technology
TTL ECL BiCMOS CMOS
ELCT 501: Digital System
Design
Winter 2011
Digital Integrated Circuits (DICs)
11 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
SSI VLSI MSI LSI ULSI
Digital Integrated Circuits
< 12 eq. gates 12-99 eq. gates 100-9999 eq.
gates
10,000-99,999
eq. gates
> 100,000 eq.
gates
ELCT 501: Digital System
Design
Winter 2011
Moore’s Law
12 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
http://www.intel.com/technology/mooreslaw/
So, we need the
Computer-aided
design (CAD)
tools!!!
ELCT 501: Digital System
Design
Winter 2011
Computer-Aided Design (CAD)
Tools
13 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
FPGA Advantage tools
Xilinx tools
Altera tools (Quartus II)
Synopsys tools
ELCT 501: Digital System
Design
Winter 2011
Design Process
14 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Required product
Define specifications
Initial design
Simulation
Design
correct?
Prototype Implementation
Testing
Meets
specifications
Finished product
Make corrections
Minor
errors?
Redesign
No No
No
Yes
Yes
Yes
ELCT 501: Digital System
Design
Winter 2011
15 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Custom-Designed Chips Programmable Logic
Devices (PLDs)
- These chips have a very general structure and
include a collection of programmable switches that
allow the internal circuitry in the chip to be
configured in many different ways.
- The designer can implement whatever functions
are needed for a particular application by choosing
an appropriate configuration of the switches.
- PLDs can be programmed multiple times
- Reprogramming might be necessary, for instance,
if a designed function is not quite as intended or if
new functions are needed that were not
contemplated in the original design.
- One of the most sophisticated types of PLD is
Field-Programmable Gate Array (FPGA) Chip
-Such chips are intended for use in specific
applications and are called Application-
Specific Integrated Circuits (ASICs) Chips
- The main advantage of a custom chip is
that its design can be optimized for a
specific task; hence it usually leads to better
performance
- It is possible to include a large amount of
logic circuitry in a custom chip than would
be possible in other types of chips.
- A disadvantage of the custom-design
approach is that manufacturing a custom
chip often takes a considerable amount of
time, on the order of months
Hardware Implementation
ELCT 501: Digital System
Design
Winter 2011
16 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
A consortium of integrated circuit manufacturers called the Semiconductor
Industry Association (SIA) produces an estimate of how the technology is expected
to evolve.
The SIA Roadmap* predicts the minimum size of a transistor that can be
fabricated on an integrated circuit chip.
the size of a transistor is measured by a parameter called its gate length will
be discussed later.
Hardware Implementation
1999 2001 2004 2006 2009 2012
Transistor gate length 0.14 µm 0.12 µm 90 nm 65 nm 50 nm 35 nm
Transistors per cm2 14
million
16
million
24
million
40
million
64
million
100
million
Chip size 800
mm2
850
mm2
900
mm2
1000
mm2
1100
mm2
1300
mm2
ELCT 501: Digital System
Design
Winter 2011
17 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
The internal layout of Intel Core i7
ELCT 501: Digital System
Design
Winter 2011
Design Evaluation
A good designer would utilize this trade-off according to the target applications
The speed of gate directly affects the max. clock speed of the digital system
Gate speed is tech-dependent. E.g. 45 nm CMOS process has faster gates than 0.18 µm.
ASIC implementation is faster than FPGA implementation
18 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Major Parameters of Digital Design Evaluation
Performance area Power
consumption
ELCT 501: Digital System
Design
Winter 2011
Summary
19 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
G=0 G=1 G=1 G=0
Transistor Switches
20 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
D
G
S
D
G
S
D
S
D
S
D
S
D
S
NMOS transistor PMOS transistor
Vf = 0 Vf = 1 Vf
CMOS logic Gates
21 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
VDD
Vx
Vx = 0
VDD
Vx = 1
VDD
x f
0 1
1 0
NOT gate
Truth Table
CMOS logic Gates (NOR Gate)
22 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
A B F
0 0 1
0 1 0
1 0 0
1 1 0
NOR gate
Truth Table
CMOS logic Gates (NAND Gate)
23 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
A B F
0 0 1
0 1 1
1 0 1
1 1 0
NAND gate
Truth Table
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