Elastic circuits Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona EMicro 2013

Elastic circuits

Jordi CortadellaUniversitat Politècnica de Catalunya, Barcelona

EMicro 2013

Goals• Convince ourselves that:

– designing an asynchronous circuit is easy– synchronous and asynchronous circuits are similar– asynchronous circuits bring new advantages

• Not to cover exotic asynchronous schemes

• Elasticity can also be synchronous

EMicro 2013 Elastic circuits 2

Clocking

EMicro 2013 Elastic circuits

Nvidia KeplerTM GK110

• How to distribute the clock?

• How to determine the clockfrequency?

• How to implement robustcommunications?

• How to reduce and manageenergy?

28nm, 7.1B transistors, 550mm2, 2688 CUDA cores,Base clock: 836MHz, Memory clock: 6GHz

Outline• Synchronous and Source-synchronous circuits• Completion detection• Handshaking• Performance analysis• Why asynchronous?• Design automation• Synchronous elasticity• Globally-asynchronous Locally-synchronous

Synchronous andSource-Synchronous

Synchronous circuit

Two competing paths:• Launching path• Capturing path

Launching path < Capturing path + Period

CLKtree + CL < CLKtree + Period

CL < Period (no clock skew)

Source-synchronous

CLKgen matched delay matched delay matched delay

• No global clock required

• More tolerance to PVT variations

• Period > longest combinational path

• Good for acyclic pipelines

Launching path

Capturing path

CLKgen

Source-synchronous with forks and joins

How to synchronize incoming events?

C element (Muller 1959)

A B C0 0 00 1 C1 0 C1 1 1

C element (Muller 1959)

A B C0 0 00 1 C1 0 C1 1 1

(many implementations exist)

Completion detection

CLKgen

fixed delay

The fixed delay must be longer than theworst-case logic delay (plus variability)

Q: could we detect when a computation has completed ASAP ?

A 1 SP 0 SP 1 SP 1 SP

Delay-insensitive codes: Dual Rail• Dual rail: every bit encoded with two signals

A.t A.f A0 0 Spacer0 1 01 0 11 1 Not used

Dual Rail AND gate

SP SP SP

SP 1 SP

1 SP SP

Dual Rail Inverter

Dual Rail AND/OR gate

Dual rail: completion detection

Dual-rail logic

•••

C done

Completion detection tree

Multi-input C element

CLKgen

CCLKgen

Dual rail: operation

CCLKgen

ResetComputeComputeComputeCompute

For a correct operation, all internal signals should be reset before the compute phase:• Use a more complex implementation of dual-rail (e.g., DIMS), or• Have internal completion detection, or• Use timing assumptions

Other DI codes• There are many DI codes:

– k-out-of n, Berger, Knuth, …

• Example: 1-out-of-4

– 2 bits with 4 wires– Same wire efficiency as DR– Less power consuming– Good for communication– Bad for logic

Wires Value0000 Spacer0001 00010 10100 21000 3

others not used

Single rail data vs. dual railSome back-of-the-envelope estimations:

Single rail Dual RailArea 1 2Delay 1 << 1Static power 1 2Dynamic power < 0.2 2

Dual rail:• Good for speed• Large area• High power comsumption

Handshaking

CLKgen unknown delay

Assume that the source module can provide data at any rate:

• When should the CLK generator send an event if the

internal delays of the circuit are unknown?

Solution: handshaking

Handshaking

I have data

I want data

Request

Acknowledge

Asynchronous elastic pipeline

ReqIn ReqOut

AckIn AckOut

• David Muller’s pipeline (late 50’s)• Sutherland’s Micropipelines (Turing award, 1989)

Multiple inputs and outputs

Mulitple inputs and outputs

Ack Req

Channel-based communication• A channel contains data and handshake wires

Single-Rail DataReq

Dual-Rail DataAck

Push/pull channels

• Push: the sender initiates the communication• Pull: the receiver initiates the communication

Sender Receiver

Single-Rail DataReq (push)

Single-Rail DataAck

Req (pull)

Four-phase protocol

• Valid data on the active edge of Req• Req/Ack must return to zero before the next transfer• Different variations of the 4-phase protocol exist

Data 1 Data 2 Data 3

Data transfer Data transfer

Two-phase protocol

• Every edge is active• It may require double-edge triggered flip-flops or

pulse generators

Data 1 Data 2 Data 3

Data transfer Data transfer

How to memorize?

CombinationalLogic LL

2-phase or 4-phase ?

How to memorize?

Pulsegenerator

2-phase

How to memorize?

CC 4-phase

Performance analysis

Ring oscillators

• Every ring requires an odd number of inverters

• The cycle period is determined by the slowest ring

• The cycle period is adapted to the operating conditions(temperature, voltage)

Global Rings

Th = 1 / 6

• Ramamoorthy and Ho, 1980Performance evaluation of asynchronous concurrent systems with Petri nets

• T. Williams et al., A self-timed chip for division, 1987• Greenstreet and Steiglitz, Bubbles can make self-timed pipelines fast, 1990• Manohar and Martin, Slack elasticity in concurrent computing, 1998.

Global Rings

Th = 2 / 6

Global Rings

Th = 3 / 6

Global Rings

Th = 1 / 6

Global Rings

0 NN/2tokens

Tokenlimited

Bubblelimited

A latch-based view of synchronous circuits

Filp-flop =Master + Slave

Multiple Rings

2 / 4 2 / 42 / 5

5 / 7 ?It’s bubblelimited !!!2 / 7

Slack matching

2 / 4 2 / 42 / 5

2 / 7 ?4 / 9

• We can add as many bubbles as we want (but not tokens!)• Slack matching can be solved optimally in polynomial time• Slack matching is conceptually equivalent to buffer (FIFO) sizing or recycling

Performance analysis

(Mean Cycle Ratio)

Latch-based design

L3L2L1 L4

Launching path

Capturing path

Matched delays can be adjustable

L3L2L1 L4

delayselection

Delays can be adjusted:

• At testing/boot time (to adjust to static variability)

• At runtime (to compensate dynamic variability)

Why asynchronous?

Exploiting elasticity

Rigidclock

Highperformance

LowenergyEMicro 2013 Elastic circuits 56

Highperformance

Exploiting elasticity

Performance

1 VRigid

2 GHz1 GHz500 MHz

Lowenergy

Rigidclock

Highperformance

Lowenergy

Voltagescaling

Voltage scaling and power savings

-24%-14%

3 ARM926 coreson the same die

Tracking variability

matched delay

Tracking variability

best typ worst

multi-corner matched delay

critical paths

Good correlation for:

• Process variability (systematic)

• Global voltage fluctuations

• Temperature

• Aging (partially)EMicro 2013 Elastic circuits 60

Margins

Gate and wire delays (typ) P V T AgingPLLJitter

Rigid Clocks:

Cycle period

Gate and wire delays (typ) P V TA

Elastic Clocks:

Cycle period

Margin reduction

Speed-up / Power savings

wasted timecomputation time

Rigid clock

computation time

Cycle period

Elastic clock

Clock elasticity

Design Automation

Design automation paradigms• Synthesis of asynchronous controllers

– Logic synthesis from Petri nets or asynchronous FSMs

• Syntax-directed translation– Correct-by-construction composition of handshake

components

• De-synchronization– Automatic transformation from synchronous to

asynchronousEMicro 2013 Elastic circuits 64

Synthesis of asynchronous controllers

DeviceLDS

LDTACK

VME BusController

DataTransceiver

BusDSr

LDTACK

Read Cycle

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

LDTACK

VME BusController

Signal Transition Graph

DTACKD

LDTACK

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

Cortadella et al., Petrify67

Syntax-directed translation

DMX <>

→→ @

áá ññ→

int = type [0..255]& gcd: main proc (in? chan <<int,int>> & out! chan int)begin x, y: var int| forever do in?<<x,y>>

; do x <> y then if x < y then y:=y-x else x:=x-y fi od

; out!x odend

Sources:

J. Kessels and A. Peeters.DESCALE: A Design Experiment for a SmartCard Application Consuming Low Energy,in Principles of Asynchronous Circuit Design, A Systems Perspective,Eds., J. Sparso and S. Furber, Kluwer Academic Publishers, 2001.

P.A.Beerel, R.O. Ozdag and M. Ferretti.A Designer’s Guide to Asynchronous VLSI,Cambridge University Press, 2010. 68

De-synchronization• Strategy: substitute the clock tree

by local clocks and handshakes

• Combinational logic and latches are not modified

• More tolerance to variability– Similar area, less power and/or more speed

• Cortadella, Kondratyev, Lavagno and Sotiriou. Desynchronization: Synthesis of asynchronous circuits from synchronous specifications.IEEE TCAD, Oct 2006.

Synchronous operation

CLKgen

Transforming a synchronous circuit into asynchronous (automatically)

De-synchronization

Transforming a synchronous circuit into asynchronous (automatically)

System-level de-synchronization

Synchronous elasticity

Different flavors of elasticity

+147 … 348201…

…Rigid

+e48…147…

201… 3

Elastic

4 38+s …147

201… Synchronous Elastic

Carloni et al., Latency-insensitive systems.

Asynchronous elasticity

Synchronous elasticity

Ring oscillator

Latch-based elasticity

sender receiver

V V V V

En En En En

Elastic netlists

ForkJoin

Join / Fork

Enable signalto data latches

Variable Latency Units

[0 - k] cycles

donego clear

V/S V/S

Globally-asynchronousLocally-synchronous

SoC design with GALS• Most IPs are synchronous

• Different components may have different operating frequencies

• Some components have variable latencies (e.g., cache hit/miss latency)

• Multiple clock domains are essential

Bridge

Fast Bus

Slow Bus

Bridge

Multiple clock domains

Single clock(mesochronous)

CLK(f0)

Rational clockfrequencies

Independent clocks

(controllable skew)

Synchronous handshakes

CLK1 CLK2

Sender ReceiverValid

• The arrival of data is unpredictable• Handshakes solve the problem

The problem: metastability

ФRФR

setup hold

How long does it take to resolve metastability?

Metastability

MTBF: Mean Time Between Failures

Classical synchronous solution

D Q D Q D Q D Q

ФT ФR

rtMTBF

Mean Time Between Failures fФ: frequency of the clock fD: frequency of the data tr: resolve time available W: metastability window : resolve time constant

# FFs MTBF

1 FF 15 min

2 FF 9 days

3 FF 23 years

Example

Handshake with synchronizers

CLK1 CLK2

Sender ReceiverValid

• Simple solution• Throughput can be highly degraded:

a long round trip for every transaction

Asynchronous FIFOs

Circular buffer

Valid Valid

Ack Ack

Data Data

Clk In Clk Out

FIFO control

• Ack is issued as soon as data has been delivered

• No impact on throughput (1 token/cycle)

• Min latency determined by the internal synchronizers

• Some tricky structures for the FIFO pointers (e.g. Grey encoding)

SoC design with GALS

Bridge

Fast Bus

Slow Bus

Bridge

• Bridges for Clock Domain Crossing usually contain asynchronous FIFOs

• Latency cost only when interfacing with synchronous domains

• No latency penalty between asynchronous domains

Conclusions• Elasticity offers flexibility in time

– Modularity– Dynamic adaptability– Tolerance to variability

• Better optimization of power/performance

• Why isn’t it an important trend in circuit design?– Lack of commercial EDA support (timing sign-off)– Designers do not feel comfortable with “unpredictable” timing– Other aspects: testing, verification, …

• De-synchronization might be a viable solutionEMicro 2013 Elastic circuits 95

Bibliography• Carmona, Cortadella, Kishinevsky and Taubin,

Elastic Circuits, IEEE Trans. On CAD, Oct. 2009.

• Beerel, Ozdag and Ferreti, A Designer’s Guide to Asynchronous VLSI, Cambridge 2001.

• Sparso and Furber, Principles of Asynchronous Circuit Design: A Systems Perspective,Kluwer 2001.

• Myers, Asynchronous Circuit Design,John Wiley&Sons, 2001

Elastic circuits Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona EMicro 2013

Documents

Success Story: Universitat Politècnica de València

Matrices Jordi Cortadella Department of Computer Science

Book Emicro Butzen

Reusing computations Jordi Cortadella Department of Computer Science

A little bit of geometry Jordi Cortadella Department of Computer Science

oincar - UPC Universitat Politècnica de Catalunya

SASTRA UNIVERSITY UNIVERSITAT POLITÈCNICA … · SASTRA UNIVERSITY UNIVERSITAT POLITÈCNICA DE CATALUNYA B.Tech in Electronics and Communication Engineering Bachelor Thesis _____

A recursive paradigm to solve Boolean relations David Bañeres Univ. Politècnica de Catalunya Jordi Cortadella Univ. Politècnica de Catalunya Mike Kishinevsky

pbutzen emicro v04 - UFRGS

transformador calculos - UPC Universitat Politècnica de

Draft - UPC Universitat Politècnica de Catalunya

Introduction to asynchronous circuit design: specification and synthesis Jordi Cortadella, Universitat Politècnica de Catalunya, Spain Michael Kishinevsky,

Data structure design Jordi Cortadella Department of Computer Science

Data types and their representation Jordi Cortadella Department of Computer Science

Numerical Simulation - UPC Universitat Politècnica de

A little bit of history Jordi Cortadella Department of Computer Science

Summary - UPC Universitat Politècnica de Catalunya

SASTRA UNIVERSITY UNIVERSITAT POLITÈCNICA DE

Jordi Cortadella, University Politècnica de Catalunya Mike Kishinevsky, Intel Corporation

Abstract - UPC Universitat Politècnica de Catalunya