EE3202 Ch11 Memory and Programmable Logic

LOGIC DESIGN

MEMORY AND PROGRAMMABLE LOGIC

EE3202 1Ertuğrul Eriş

EE33201 COURSE ASSESMENT MATRIX

LOGIC DESIGN LEARNING OUTCOMES a b c d e f g h i j k

Will employ Boolean Algebra in logic circuits modelling.

3 3     3     1     2

Wiil carry out aritmetic operations by using 2’s complement reperesentation of negative numbers

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Will analyse Logic Circuits which include Small Scale Integrated components, by using various methods.

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Will design logic circuits which include small scale integrated components, by using various methods.

3 3     3     1     2

Will analyse logic circuits which include medium scale integrated components, by using various methods.

3 3     3     1     2

Will design logic circuits which include medium scale integrated components, by using various methods.

3 3     3     1     2

Will analyse logic circuits which include large scale integrated components, by using various methods.

3 3     3     1     2

Will design logic circuits which include large scale integrated components, by using various methods.

3 3     3     1     2

Will simulate logic circuits by employing " proteus" as a tool.

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CONVENTIONAL AND ARRAY LOGIC DIAGRAMS FOR OR GATE

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BLOCK DIAGRAM OF A MEMORY UNIT

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CONTENTS OF A 1024 X 16 MEMORY

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Is this sequential? State diagram? Mathematical model?

CONTROL INPUTS TO MEMORY CHIP

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MEMORY CYCLE TIMING WAVEFORMS

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MEMORY CELL

SRAM (Static RAM): Requires 6 transistorsDRAM (Dynamic RAM): Requires a single MOS transistor and and a capacitor, Low power

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DIAGRAM OF A 4 X 4 RAM

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TWO-DIMENSIONAL DECODING STRUCTURE FOR A 1K-WORD MEMORY

Single Dimention Decoder

Two Dimention

Decoder

Number of AND gates

1024 64

AND gates inputs

10 5

Adsress bits

10 10

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ADDRESS MULTIPLEXING FOR A 64K (216) DRAM

• Two dimentional Decoding: 16 address-bit input• Address multiplexing: 8 address-bit input in the IC package

CAS: Column Address StrobeRAS: Row Adsress Strobe

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Bir önce devre ile bu devrenin karşılaştırılması:• Bacak sayısıGeçikme

ROM BLOCK DIAGRAM

k: Number of address bits2k: Number of address, number of n-bit-words stored2k x n = Number of connections between AND and OR gates

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INTERNAL LOGIC OF A 32 X 8 ROM

k: Number of address bits = 52k: Number of address, number of n-bit-words stored = 32, n = 82k x n = 32 x 8 = 256 connections

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PROGRAMMING THE ROM

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ROM IMPLEMENTATION OF COMBINATIONAL CIRCUITS

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BASIC CONFIGURATION OF THREE PLDs

PLD: Programmable Logic Devices: Combinational, Sequentials

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PLA WITH THREE INPUTS, FOUR PRODUCT TERMS, AND TWO OUTPUTS

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PLA SECOND EXAMPLE F1(A, B, C) = Σ (0, 1, 2, 4)F2(A, B, C) = Σ (0, 5, 6, 7)

F1 = (AB + AC+ BC)’ F2 = AB + AC+ A’B’C’

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PLA SIZE PROGRAMMING n inputs, k product terms, m outputs n buffer-inventor gates, k AND gates, m OR gates,

m XOR gates 2n x k connections between and AND array gates k x m connections between AND and OR gates m connections with the XOR gates Typical: n = 16, k = 48, m = 8 Programming

Mask programmable PLA Field programmable PLA

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PAL WITH FOUR INPUTS, FOUR OUTPUTS, AND A THREE-WIDE AND-OR STRUCTURE

• Typical: Four inputs, four outputsFour sections: three wide AND-OR

• Commercial: eigth inputs, eight outputs, eigth section: eigth-wide ABD_OR array

In designing with Pal, The Boolean functions must beSimplified to fit into each section

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FUSE MAP FOR PAL AS SPECIFIED IN THE TABLE

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w(A, B, C, D) = Σ (2,12,13)x(A, B, C, D) = Σ (7,8,9,10,11,12,13,14,15)y(A, B, C, D) = Σ (0,2,3,4,5,6,7,8,10,11,15)z(A, B, C, D) = Σ (1,2,8,12,13)

w = ABC’ + A’B’CD’x = A + BCDy = A’B + CD + B’D’z = ABC’ + A’B’CD’ +AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D

SEQUENTIAL PROGRAMMABLE LOGIC DEVICE

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BASIC MACROCELL LOGIC

OE: Output enable controls three state output buffer

A typical SPLD 8 to 10 macrocells within one IC package

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GENERAL CPLD CONFIGURATION

• (I/O) blocks provide connections to the IC pins. • Each I/O pin is driven by a three state buffer and can be programmed to act as input or output.• The switch matrix receives inputs from I/O the block and directs them to the individual macrocells.• Selected outputs from macrocells are sent to the outputs as required.• unused product terms can be used by other nearby macrocells.• PLDs sometimes called ‘function blocks’

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FPGA (FIELD PROGRAMMABLE GATE ARRAY)

Typical FPGA logic block consists of lockup tables, multiplexers, gates, and flip-flops. A lookup table is a truth table stored in an SRAM and provides the combinational circuit functions for the logic block.

Combinational logic section, along with a number of programmable multiplexers, is used to configure the input equations for the flip-flop and the output of the logic block.

Different firm different configurations Requires extensive CAD tools to facilitate synthesis

procedure HDL (Hardware Description Language): ABEL, VHDL,

Verilog

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BASIC ARCHITECTURE OF XILINX SPARTAN AND PREDECESSOR DEVICES

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CLB: Configurable logic blockIOB: Input/Output block

CLB(CONFIGURABLE LOGIC BLOCK) ARCHITECTURE

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CLB ARCHITECTURE CLB (configurable Logic Block) consists of

Look up table, muxs, registers, paths for control signals F, G function generators

Look up tables, generate any four varible function

H function block Can Get its input from look up tables or from external inputs

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CELL CONTROLLING A PIP TRANSMISSION GATE

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CIRCUIT FOR A PROGRAMMABLE PIP

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XC4000 SERIES IOB

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DISTRIBUTED RAM CELL FORMED FROM A LOCKUP TABLE

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SPARTAN DUAL-PORT RAM

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ATRIBUTES OF THE XILINX SPARTAN XL DEVICE FAMILY

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SPARTAN 11 DEVICE ATTRIBUTES

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COMPARISON OF THE SPARTAN DEVICE FAMILIES

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SPARTAN II ARCHITECTURE

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SPARTAN 11 CLB SLICE

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SPARTAN II IOB

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VIRTEX II OVERALL ARCHITECTURE

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VIRTEX IOB BLOCK

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PROGRAM OUTCOMES

PROGRAM DESIGN

??? CIRCICULUM

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??? CIRCICULUM

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Std. questionnaire

Std. questionnaire

Std. questionnaire

STUDENT PROFILE

DEPT, PROGRAM

STUDENTNEWCOMER

STUDENT

QUALITY IMP. TOOLS

EXTRERNAL CONSTITUENT

FACULTY

GOVERNANCE

INTRERNAL CONSTITUENT

STUDENT,

STATE, ENTREPRENEUR

ALUMNI, PARENTS

NGO

GOAL: NATIONAL/INTERNATIONAL ACCREDITION

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U/N

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ALI

FIC

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EU/NATIONAL

GRADUATE

STUDENT

QUESTIONNAIRES

FIELD QUALIFICATIONS

KNOWLEDGE

SKILLS

COMPETENCES

EXTRERNAL CONSTITUENT REQUIREMENTS

ORIENTIATION

ORIENTIATION

PROGRAM OUTCOMES

PROGRAM

OUTCOMES

PROGRAM

OUTCOMES

FIELDQALIFICATIONS

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BLOOM’S TAXONOMYANDERSON AND KRATHWOHL (2001)

July 2011 Ertuğrul Eriş 43

http://www.learningandteaching.info/learning/bloomtax.htm

!!Listening !! Doesn’t exits in the original!!!

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TÜRKİYE YÜKSEKÖĞRETİM ULUSAL YETERLİKLER ÇERÇEVESİ (TYUYÇ)

TYUYÇDÜZEYİ

BİLGİ- Kuramsal- Uygulamalı

BECERİLER- Kavramsal/Bilişsel- Uygulamalı

KİŞİSEL VE MESLEKİ YETKİNLİKLER

Bağımsız Çalışabilme ve Sorumluluk

Alabilme Yetkinliği

Öğrenme Yetkinliği

İletişim ve Sosyal Yetkinlik

Alana Özgü ve Mesleki Yetkinlik

6LİSANS

_____

EQF-LLL:6. Düzey

_____

QF-EHEA:1. Düzey

- Ortaöğretimde kazanılan yeterliklere dayalı olarak alanındaki güncel bilgileri içeren ders kitapları, uygulama araç –gereçleri ve diğer bilimsel kaynaklarla desteklenen ileri düzeydeki kuramsal ve uygulamalı bilgilere sahip olmak

- Alanında edindiği ileri düzeydeki kuramsal ve uygulamalı bilgileri kullanabilmek,

- Alanındaki kavram ve düşünceleri bilimsel yöntemlerle inceleyebilmek, verileri yorumlayabilmek ve değerlendirebilmek, sorunları tanımlayabilmek, analiz edebilmek, kanıtlara ve araştırmalara dayalı çözüm önerileri geliştirebilmek.

- Uygulamada karşılaşılan ve öngörülemeyen karmaşık sorunları çözmek için bireysel ve ekip üyesi olarak sorumluluk alabilmek,

- Sorumluluğu altında çalışanların mesleki gelişimine yönelik etkinlikleri planlayabilmek ve yönetebilmek

- Edindiği bilgi ve becerileri eleştirel bir yaklaşımla değerlendirebilmek, öğrenme gereksinimlerini belirleyebilmek ve öğrenmesini yönlendirebilmek.

- Alanıyla ilgili konularda ilgili kişi ve kurumları bilgilendirebilmek; düşüncelerini ve sorunlara ilişkin çözüm önerilerini yazılı ve sözlü olarak aktarabilmek,

- Düşüncelerini ve sorunlara ilişkin çözüm önerilerini nicel ve nitel verilerle destekleyerek uzman olan ve olmayan kişilerle paylaşabilmek,

- Bir yabancı dili kullanarak alanındaki bilgileri izleyebilmek ve meslektaşları ile iletişim kurabilmek (“European Language Portfolio Global Scale”, Level B1)

- Alanının gerektirdiği düzeyde bilgisayar yazılımı ile birlikte bilişim ve iletişim teknolojilerini kullanabilmek (“European Computer Driving Licence”, Advanced Level).

- Alanı ile ilgili verilerin toplanması, yorumlanması, duyurulması ve uygulanması aşamalarında toplumsal, bilimsel ve etik değerlere sahip olmak,

- Sosyal hakların evrenselliğine değer veren, sosyal adalet bilincini kazanmış, kalite yönetimi ve süreçleri ile çevre koruma ve iş güvenliği konularında yeterli bilince sahip olmak.

ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ

BLOOMS TAXONOMY

October 2011 Ertuğrul Eriş

COURSE ASSESMENT MATRIX

EE3202 LOGIC DESIGN a b c d e f g h i j k

1. Will employ Boolean Algebra in logic circuits modelling. 3 3 3 3

2. Will analyse Logic Circuits which include Small Scale Integrated components, by using various methods.

3 3 3 3 1 3

3. Will design logic circuits which include small scale integrated components, by using various methods.

3 3 3 3 1 3

4. Will analyse logic circuits which include medium scale integrated components, by using various methods.

3 3 3 3 1 3

5. Will design logic circuits which include medium scale integrated components, by using various methods.

3 3 3 3 1 3

6. Will analyse logic circuits which include large scale integrated components, by using various methods.

3 3 3 3 1 3

7. Will design logic circuits which include large scale integrated components, by using various methods.

3 3 3 3 1 3

8. Will simulate combinational logic circuits by employing " proteus" as a tools.

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1. Will employ Boolean Algebra in logic circuits modelling.3 3 3 3 1 3

EE3202 Ertuğrul Eriş 45

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