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EE241 Spring 2011EE241 - Spring 2011Advanced Digital Integrated Circuits
Lecture 21: Dynamic Logic
Announcements
Homework #4 due next Monday
Quiz #4 next Monday
Final exam next Wedensday!
Reading: Chapter 8 in the Bowhill text (by Gronowski)
Background material from Rabaey 2nd ed Chapters 6 10
2
Background material from Rabaey, 2 ed, Chapters 6,10
2
Outline
Last lectureOptimal supplies and thresholds
Pass-transistor logic
This lectureDomino logic
3
Domino LogicDomino Logic
3
Dynamic Logic
VDD VDD
Mp
M
PDN
In1In2
In3
OutMe
M
PUN
In1In2
In3
Out
CL
CL
5
Me Mp L
p networkn network
2 phase operation:• Evaluation
• Precharge
Dynamic Logic
Advantages:FastCompactCompact
Need to watch out for:PowerNoise marginsCharge leakageCharge sharing
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Charge sharingNoise couplingCharge injectionCascading dynamic gates
4
Logical Effort
In
Out
7LE =
Logical Effort
Out
Out
8LE =
LE =
5
Charge Leakage
9Courtesy of IEEE Press, New York. 2000
ILeak = (IN sub + IN diode) – (IP sub + IP diode)
Time to switch the next gate: tsw = (CDYN * Vsw)/ILeak
Limits the minimum frequency:fmin = 1/(tsw * #phases per clk cycle)
Compensating Leakage
10
6
Charge Sharing (Redistribution)
VDD case 1) if Vout < VTn
MpOut
ACL
C
MaX
CLVDD CLVout t Ca VDD VTn VX – +=
or
Vout Vout t VDD–CaCL-------- VDD VTn VX – –= =
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Me
B = 0Ca
Cb
Mb
Vout VDD
CaCa CL+----------------------
–=
case 2) if Vout > VTn
Charge Sharing - Solutions
VDDVDD
Mp
Out
A
B
Ma
Mb
Mbl MpOut
A
B
Ma
Mb
Mbl
12
Me Me
(b) Precharge of internal nodes(a) Static bleeder
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Clock Feedthrough
VDD
MpOut
ACL
Ca
MaX
2.5V
h t
13
Me
B Ca
Cb
Mb overshoot
out
Miller and Back-gate Coupling
14Courtesy of IEEE Press, New York. 2000
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Capacitive Coupling
15Courtesy of IEEE Press, New York. 2000
Capacitive Coupling
Dynamic node: Static node:
16Courtesy of IEEE Press, New York. 2000
9
Capacitive Coupling
Lateral coupling: Shielding
17Courtesy of IEEE Press, New York. 2000
Minority Charge Injection
18Courtesy of IEEE Press, New York. 2000
10
Supply Noise
19Courtesy of IEEE Press, New York. 2000
Domino LogicDomino Logic
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Cascading Dynamic Gates
VDD VDD
V
Mp Mp
In
Out1 Out2
Out2
Out1
In
V
VTn
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Me Me t
(a) (b)
Only 01 Transitions allowed at inputs!
Cascading Dynamic Logic
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12
Domino Logic
VDD VDD
VDD
Mp
PDN
In1
In2
In3
Out1Mp
PDN
In4
Out2
Mr
Static Inverterwith Level Restorer
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Me Me
Krambeck et al, JSSC 6/82
Logical Effort
Inverter pair:
In
Out
Skewed inverter pair:
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LE =
13
Logical Effort
Out
25
LE =
Designing with Domino Logic
VDD VDD
V
Mp
PDN
In1
In2
Out1Mp
PDN
In4
Out2
Mr
VDD
26
Me
In3
Me
Inputs = 0during precharge
Can be eliminated!
14
Logical Effort
Out
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LE =
Delayed Precharge
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15
IBM’s 1GHz Processor
Silberman et al, ISSCC’98JSSC 11/98JSSC 11/98
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Example: 240ps adder
pc1 pc2 pc3 pc4 psel
Clock Generator
pc1
scan_in
footed domino
footless domino
static CMOShard edgeinputs
t, g gen H4 I4 H16 I16 H64
Sum precompute
SumselectMUX
pc1 pc2 pc3 pc4 psel
sumMUX OutFF
pc1Scan chain
Scan chain
S0
S1
Buffer
Com
parator
Out
H64
H64'
Precomputed sums
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Precomputed sums
Kao, ISSCC’06
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Layout Floorplan
TG H4 H16J1 SUM SELECT
XX
OR
2
XO
R2
XO
R2
X
K1
J024 TRACKS
LEGEND
I16I4 H64TG SUM SELECT
TG H4
I16I4
H16
H64
J1
TG SUM SELECT
SUM SELECT
XO
R2
XO
R2
XO
R2
XO
R2
XO
R2
XO
R2
XO
R2
J1J0
EVERYBITSLICE
SPARSE-2CARRYTREE
SPARSE-2SUM
PRECOMP
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pc1
TCYCLE DUTYCYCLE
24%
Timing Diagram
pc2
pc3
pc4
psel
H64
Can only evaluateafter inputs have
settled
43%
53%
53%
45%
32
H64
H64'
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Domino Properties
Logic evaluation propagates as falling dominoes
Evaluation period determines the logic depth
The nodes must be precharged during the precharge period (can limit the minimum size of PMOS)
Inputs must be stable (or have only one rising transition) during the evaluation
Gates are ratioless
33
Gates are ratioless
Restorer is ratioed
All the gates are non-inverting
Only one transition to be optimized
Logic Design Problem
How to design an XOR/MUX without a complementary signal available?We need it in datapathsWe need it in datapathsIf the logic is followed by a flip-flop, or a latch with a hard edge, can use complementary or pass-transistor logicDomino logic is used with latches, and a new domino stage may follow the XOR
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stage may follow the XORSolutions:
Use dual-rail domino (dynamic CVSL)Violate some of domino rules (but still design a reliable circuit)Force a hard edge
18
Sum Implementation (1)
Clk
VDD
Clkd
VDDKeeper
Gi:0
Clk
Clk
Clkd
Si0
Sum
35Clk
Gi:0
Si1
[Shimazaki, ISSCC’03]
Sum Implementation (2)
36
[Anders et al, ISSCC’02]
19
Sum Implementation (3): Strobing
37
[Park, VLSI’00]
VDD VDD
Differential (Dual Rail) Domino
MpCLK
A
B
M1
M2
A B
Mp CLK
O = ABO = AB
Mf1 Mf2
38
MeCLK
B M2
Dynamic CVSL (Clock CVSL) - Heller et al, ISSCC’84
20
Domino TimingDomino Timing
Latch-Based Timing
SkewStatic logic
L1Latch
Logic
Logic
L2Latch
L1 latch
L2 latch
Long
40
Can tolerate skew!
Longpath
Shortpath
21
Dynamic Logic with Latches
41
Edges become hardTime available to logic is P – 2TD-Q From [Harris]
Latches with Dynamic Logic
Clock evaluates logic
Phase1-dominoevaluates
Phase2-dominoprecharges
L2 latchL1 latch
C oc e a uates og cand opens subsequent latch:
Static signals driving dynamiclogic must be eithernon-inverting orstable before evaluation
p g
42
Shortpath
Phase1-dominoprecharges
Phase2-dominoevaluates
22
Skew-Tolerant Domino
General Reference:Harris, Horowitz, “Skew-tolerant domino circuits” Harris, Horowitz, Skew tolerant domino circuits
ISSCC’97, JSSC 11/97
Also slides from D. Harris’s Web site:
43
http://www3.hmc.edu/~harris/index.html
Domino Logic with Latches
44
Time available to logic is P – 2TD-Q
23
Clock Skew
45Time penalty: TL = P – (2TD-Q + 2Tsk)
Non-Balanced Phase Delays
46Time penalty: TL = P – (2TD-Q + 2Tsk) - Timbal
24
Skew-Tolerant Domino
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Overlap clocks:• x evaluates before y precharges • implicit latch between 1 and 2• no need for latch between domino phases
From [Harris]
Multiple Phases
48
25
Precharge Phase
49
Evaluation Phase
50
26
Next Lecture
Adders
51
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