ECO Timing Optimization Using Spare Cells Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang ICCAD2007,...

ECO Timing Optimization ECO Timing Optimization Using Spare CellsUsing Spare Cells

Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen ChangYen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang

ICCAD2007, Pages 530-535ICCAD2007, Pages 530-535

OutlineOutline

IntroductionIntroduction Problem FormulationProblem Formulation The Spare-Cell Selection AlgorithmThe Spare-Cell Selection Algorithm Experimental ResultsExperimental Results ConclusionsConclusions

OutlineOutline

IntroductionIntroduction Problem FormulationProblem Formulation The Spare-Cell Selection AlgorithmThe Spare-Cell Selection Algorithm Experimental ResultsExperimental Results ConclusionsConclusions

IntroductionIntroduction

Spare cells are often used to perform ECO (Engineering Change Order) after the placement stage to change/fix a design.

They are often evenly placed on the chip layout; the type and number of spare cells vary from different chip designs and are usually determined by designers empirically.

IntroductionIntroduction

Using spare cells is an efficient way to do Using spare cells is an efficient way to do netlist changes.netlist changes. Save time and effort of re-placing the netlistSave time and effort of re-placing the netlist Save production cost of masksSave production cost of masks

OutlineOutline

IntroductionIntroduction Problem FormulationProblem Formulation The Spare-Cell Selection AlgorithmThe Spare-Cell Selection Algorithm Experimental ResultsExperimental Results ConclusionsConclusions

Problem FormulationProblem Formulation

A timing path is defined as A timing path is defined as (1) A path from a primary input to a primary output(1) A path from a primary input to a primary output

(2) A path from a primary input to a flip-flop input(2) A path from a primary input to a flip-flop input

(3) A path from a flip-flop output to a primary output(3) A path from a flip-flop output to a primary output

(4) A path between a flip-flop output and a flip-flop input(4) A path between a flip-flop output and a flip-flop input

An ECO path is a timing path that violates An ECO path is a timing path that violates the timing constraint.the timing constraint.

Problem FormulationProblem Formulation

A buffering operation is to insert a buffer-type spA buffering operation is to insert a buffer-type spare cell gare cell gSS(i) into a net n(i) into a net nEE(j) along an ECO path. (j) along an ECO path.

A gate sizing operation is to exchange a spare cA gate sizing operation is to exchange a spare cell gell gSS(i) with a gate g(i) with a gate gEE(j) along an ECO path by r(j) along an ECO path by rewiring.ewiring.

OutlineOutline

IntroductionIntroduction Problem FormulationProblem Formulation The Spare-Cell Selection AlgorithmThe Spare-Cell Selection Algorithm Experimental ResultsExperimental Results ConclusionsConclusions

Timing Model and PropertiesTiming Model and Properties Synopsys Liberty library formatSynopsys Liberty library format

Use lookup table to calculate gate delays.Use lookup table to calculate gate delays. The gate delay and the output transition time are functions The gate delay and the output transition time are functions

of the output loading and the input transition time.of the output loading and the input transition time.

Timing Model and PropertiesTiming Model and Properties Loading dominanceLoading dominance

The effect of its output capacitance to the gatThe effect of its output capacitance to the gate delay is much larger than that of the input tre delay is much larger than that of the input transition time .(28x vs 1x)ansition time .(28x vs 1x)

Shielding effectShielding effect Change of the netlist effects delay of neighbor Change of the netlist effects delay of neighbor

gates only. gates only.

Algorithm OverviewAlgorithm Overview

Buffer InsertionBuffer Insertion

We keep the solution if d’(gE(M−1))+d’(gS(j)) < d(gE(M−1)) , M: size of GE

Gate SizingGate Sizing

Spare-Cell Selection inside a Spare-Cell Selection inside a Bounding PolygonBounding Polygon

Let the width of the square bounding box of gE(i) centered at gE(i) be

Let the width of the square bounding box of g(j) (g(j) ∈ G(j)) centered at g(j) be

: the capacitance per unit wirelengthCEO(i) : the output pin capacitance of gate gE(i).FO(gE(i)) : the set of fan-out gates of gE(i)G(j) : the fan-outs of the gate gE(i) to be sized

Spare-Cell Selection inside a Spare-Cell Selection inside a Bounding PolygonBounding Polygon

Spare-Cell Selection inside a Spare-Cell Selection inside a Bounding PolygonBounding Polygon

Spare-Cell Selection inside a Spare-Cell Selection inside a Bounding PolygonBounding Polygon

Let the width of the square bounding box of g(k) (g(k) G∈ (k)) centered at g(k) be

Let the width of the square bounding box of g(j) (g(j) G∈ (j)) centered at g(j) be

G(k) : the fan-ins of the gate gE(i) to be sizedG(j) : the fan-outs of the gate gE(i) to be sized

Solution ControlSolution Control

For each set of solutions, we keep at most For each set of solutions, we keep at most kk solutions. ( solutions. (kk is a user-defined parameter) is a user-defined parameter) Discard non-dominant solutions.Discard non-dominant solutions. Classify these solutions by the number of used bufferClassify these solutions by the number of used buffer

s.s. Keep the best K solutions for each class. Keep the best K solutions for each class.

OutlineOutline

IntroductionIntroduction Problem FormulationProblem Formulation The Spare-Cell Selection AlgorithmThe Spare-Cell Selection Algorithm Experimental ResultsExperimental Results ConclusionsConclusions

Shielding EffectShielding Effect

Shielding EffectShielding Effect

ECO Timing OptimizationECO Timing Optimization

ECO Timing OptimizationECO Timing Optimization

OutlineOutline

IntroductionIntroduction Problem FormulationProblem Formulation The Spare-Cell Selection AlgorithmThe Spare-Cell Selection Algorithm Experimental ResultsExperimental Results ConclusionsConclusions

ConclusionsConclusions

This paper present the first work for this problem of ECO timing optimization using spare-cell rewiring.

They didn’t solve the competition for using a spare cell among multiple paths.

They can’t insert multiple buffers in a single net.

ThanksThanks

Timing Model and PropertiesTiming Model and Properties

Output loading consists ofOutput loading consists of input pin capacitanceinput pin capacitance output pin capacitanceoutput pin capacitance wire loadingwire loading

c : is the capacitance per unit wirelength,FO(g(i)) : the set of fan-out gates of g(i)CO(i) : output pin capacitance of gate g(i)CI (j) : input pin capacitance of the fan-outs of the gate g(i)

Gate Sizing and Buffer InsertionGate Sizing and Buffer Insertion

Buffering on the net nE(i) changes the delay of the driving gate and driven gates of nE(i), while other gates are little or not affected. Thus the impact of buffering on the timing of the ECO path is the delay change of gE(i), gE(i + 1), and the delay increase of the inserted buffer.

Sizing the gate gE(i) changes the delay of the fan-in/fan-out gates of gE(i), while other gates are little or not affected. Thus the impact of sizing gE(i) on the timing of the ECO path is the delay change of gE(i − 1), gE(i + 1), and the sized gate.

Gate SizingGate Sizing

We keep the solution if

d’(gE(M −2))+d’(gS(j)) < d(gE(M − 2))+d(gE(M −1)),and

d’(gE(M −2)) < d(gE(M −2)),

Spare-Cell Selection inside a Spare-Cell Selection inside a Bounding PolygonBounding Polygon

Theorem 1: Given a net nE(i) with the source gE(i) and the sinks in G(j) to be buffered, inserting any buffer-type spare cell, whose output transition time is not smaller than gE(i) and with the same output loading, outside the bounding polygon Γ(i) into the net increases the path delay.