ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS

DESIGN

Lecture 13

Dr. Shi

Dept. of Electrical and Computer Engineering

SEQUENTIAL CIRCUITS: LATCHES

Overview

Circuits require memory to store intermediate data

Sequential circuits is a circuit that has memory Flip-flop and latch Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM)

Sequential circuits use a clock signal to determine when to store values.

The story so far ...

Combinational circuits No way of remembering or storing

information after inputs have been removed.

To handle this, we need sequential logic capable of storing intermediate (or final) results.

Sequential Circuits

Combinational circuit

Flip Flops

OutputsInputs

Nextstate Present

state

Clock

Clock: a periodic external signalClock: a periodic external signal

synchronizes when states change makes it easier to design and build large

systems

synchronizes when states change makes it easier to design and build large

systems

Cross-coupled Inverters

0

1

1

0

State 0 State 1

The system has two stable states A stable value can be stored at

inverter outputs Not possible to set a desired state

Cross-coupled Inverters (cont.)• This circuit has no stable states

Y X Z

XZ

ZY

YX

XXZYX

Time0

X

Y

Z

'1'

'0'

2 3 6 754 8 9 10 11

SR Latch

S-R Latch with NORs

1 11 00 10 0

S R Q Q’

0 1

1 0 Set

1 0Stable

0 1 Reset

0 0 Forbidden

R (reset)

Q

Q

S (set)

S-R latch made from cross-coupled NORs If Q = 1, set state If Q = 0, reset state

S=1 and R=1 generates unpredictable results

reset

setS

R

Q

Q

S-R Latch with NORs

1 11 00 10 0

S R Q Q’

0 1

1 0 Set

1 0Stable

0 1 Reset

0 0 Forbidden

R (reset)

Q

Q

S (set)

S

R

Q

Q

tpd

S-R Latch with NORs

1 11 00 10 0

S R Q Q’

0 1

1 0 Set

1 0Stable

0 1 Reset

0 0 Forbidden

R (reset)

Q

Q

S (set)

What happens if both inputs R and S simultaneously change from 0 to 1?

Race conditions: See who runs faster

S-R Latch with NANDs

S

R

Q

Q’

0 00 11 01 1

S R Q Q’

0 1

1 0 Set

1 0 Store

0 1 Reset

1 1 Forbidden

Latch made from cross-coupled NANDsSometimes called S’-R’ latchUsually S=1 and R=1S=0 and R=0 generates unpredictable results

S-R Latches

Latch operation Latch operation enabled byenabled by

CC

Latch operation Latch operation enabled byenabled by

CC

Input sampling

enabled by gatesInput sampling

enabled by gates

NOR S-R Latch with Control Input

R’

S’Q’

Q

C’

Outputs change Outputs change when C is low:when C is low:RESET and SETRESET and SET

Otherwise: HOLDOtherwise: HOLD

Outputs change Outputs change when C is low:when C is low:RESET and SETRESET and SET

Otherwise: HOLDOtherwise: HOLD

Latch is Latch is level-sensitivelevel-sensitive, in regards to C, in regards to CLatch is Latch is level-sensitivelevel-sensitive, in regards to C, in regards to C

Only stores data if C’ = 0Only stores data if C’ = 0

S-R Latch with control input

Occasionally, desirable to avoid latch changesC = 0 disables all latch state changesControl signal enables data change when C = 1Right side of circuit same as ordinary S-R latch.

D-Latch

D Latch

Q

Q’

C

D S

R

X

Y

X Y C Q Q’

0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 Q0’ Store

0 1 0 11 1 1 0X 0 Q0 Q0’

D C Q Q’

Q0 indicates the previous state (the previously stored value)

D Latch

Q

Q’

C

D S

R

X

Y

0 1 0 11 1 1 0X 0 Q0 Q0’

D C Q Q’

Input value D is passed to output Q when C is highInput value D is ignored when C is low

D Latch

E

x

Latches on following edge of clock

E

D Q

C

x

z

z

The D latch stores data indefinitely, regardless of input D values, if C = 0

Forms basic storage element in computers

Symbols for Latches

SR latch is based on NOR gatesS’R’ latch based on NAND gatesD latch can be based on either.D latch sometimes called transparent latch

Disadvantage of Transparent Latches

D

G

Q D

G

QD

G

Q QD

G

Problems:When G=1, D passes through the entire chairWhen G=1, any glitches of D passes through the entire circuit

Problems:When G=1, D passes through the entire chairWhen G=1, any glitches of D passes through the entire circuit

Master-Slave D Flip FlopConsider two latches combined togetherOnly one C value active at a timeOutput changes on falling edge of the clock

always @(negedge clk) begin Q=D; end

0 1 0 11 1 1 0X 0 Q0 Q0’

D C Q Q’

Positive and Negative Edge D Flip-FlopD flops can be triggered on positive or negative edgeBubble before Clock (C) input indicates negative edge trigger

Lo-HiLo-Hi edge Hi-LoHi-Lo edge

Clocked D Flip-FlopStores a value on the positive edge of CInput changes at other times have no effect on output

T Flip-Flop

Positive Edge-Triggered T Flip-Flop

0 Q0 Q0’

1

Q Q’C T Created from D flopT=0 -> keep currentK resetsT=1 -> invert current

Q’0 Q0

JK Flip-Flop

Positive Edge-Triggered J-K Flip-Flop

0 0 Q0 Q0’ 0 1 0 1 1 0 1 0 1 1 TOGGLE

Q J Q’CLK K Created from D flopD = JQ’+K’QJ setsK resetsJ=K=1 invert output

Clocked J-K Flip FlopTwo data inputs, J and KJ -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

Asynchronous Inputs

Asynchronous Behavior

• Synchronous behavior

• Effects on the output are synchronized with the CLK input.

• Asynchronous behavior

• Effects on the output are synchronized with the CLK.

•Only used for set/reset

Asynchronous Inputs

Asynchronous Inputs

• Note reset signal (R) for D flip flop

• If R = 0, the output Q is cleared

•This event can occur at any time, regardless of the value of the CLK

Summary

Flip flops are powerful storage elements They can be constructed from gates and latches!

D flip flop is simplest and most widely used Asynchronous inputs allow for clearing and

presetting the flip flop output Multiple flops allow for data storage

The basis of computer memory! Combine storage and logic to make a computation

circuit Next time: Analyzing sequential circuits.