ECE 667 - Synthesis & Verification - Implementation 1 ECE 667 Spring 2007 ECE 667 Spring 2007...

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ECE 667 - Synthesis & Verification - Implementation

ECE 667ECE 667Spring 2007Spring 2007

Synthesis and Verificationof Digital Circuits

Design ImplementationDesign Implementation

ECE 667 - Synthesis & Verification - Implementation 2

Implementation ChoicesImplementation Choices

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches

ECE 667 - Synthesis & Verification - Implementation 3

The Custom Approach The Custom Approach

Intel 4004

Courtesy Intel

ECE 667 - Synthesis & Verification - Implementation 4

Transition to Automation and Regular StructuresTransition to Automation and Regular Structures

Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel

ECE 667 - Synthesis & Verification - Implementation 5

Intel Pentium (IV) microprocessorIntel Pentium (IV) microprocessor

ECE 667 - Synthesis & Verification - Implementation 6

Cell-based Design (or standard cells)Cell-based Design (or standard cells)

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cellR

ow

s o

f ce

lls

ECE 667 - Synthesis & Verification - Implementation 7

Standard Cell Layout Methodology – 1980sStandard Cell Layout Methodology – 1980s

signals

Routingchannel

VDD

GND

ECE 667 - Synthesis & Verification - Implementation 8

Standard Cell – The New GenerationStandard Cell – The New Generation

Cell-structurehidden underinterconnect layers

ECE 667 - Synthesis & Verification - Implementation 9

Standard Cell - ExampleStandard Cell - Example

3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time

ECE 667 - Synthesis & Verification - Implementation 10

Automatic Cell GenerationAutomatic Cell Generation

Courtesy Acadabra

Initial transistorgeometries

Placedtransistors

Routedcell

Compactedcell

Finishedcell

ECE 667 - Synthesis & Verification - Implementation 11

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Array based designArray based design

ECE 667 - Synthesis & Verification - Implementation 12

Gate Array — Sea-of-gatesGate Array — Sea-of-gates

rows of

cells

routing channel

uncommitted

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)

ECE 667 - Synthesis & Verification - Implementation 13

Sea-of-gate Primitive CellsSea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation

ECE 667 - Synthesis & Verification - Implementation 14

A Historical Perspective: the PLAA Historical Perspective: the PLA

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1

ECE 667 - Synthesis & Verification - Implementation 15

Two-Level LogicTwo-Level Logic

Inverting format (NOR-NOR) more effective

Every logic function can beexpressed in sum-of-productsformat (AND-OR)

minterm

ECE 667 - Synthesis & Verification - Implementation 16

Programmable Logic ArrayProgrammable Logic Array

GND GND GND GND

GND

GND

GND

VDD

VDD

X0X0 X1 f0 f1X1 X2X2

AND-plane OR-plane

Pseudo-NMOS PLA

ECE 667 - Synthesis & Verification - Implementation 17

““Soft” MacroModulesSoft” MacroModules

Synopsys DesignCompiler

ECE 667 - Synthesis & Verification - Implementation 18

““Intellectual Property”Intellectual Property”

A Protocol Processor for Wireless

ECE 667 - Synthesis & Verification - Implementation 19

Semicustom Design FlowSemicustom Design Flow

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

Des

ign

Iter

atio

nD

esig

n It

erat

ion

ECE 667 - Synthesis & Verification - Implementation 20

The “Design Closure” ProblemThe “Design Closure” Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)