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ECE 331 – Digital System Design
Constraints in Logic Circuit Design
(Lecture #14)
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Fall 2010 ECE 331 - Digital System Design 2
Material to be covered …
Supplemental
Chapter 8: Sections 1 – 5
Fall 2010 ECE 331 - Digital System Design 3
Power Consumption
Fall 2010 ECE 331 - Digital System Design 4
Power Consumption• Each integrated circuit (IC) consumes power
• Power consumption can be divided into two parts:
– Static power consumption (PS)
– Dynamic power consumption (PD)
• Total power consumption (PT) can then be determined as
– PT = PS + PD
Fall 2010 ECE 331 - Digital System Design 5
Static Power Consumption
• PS = V
CC * I
CC
– VCC
= supply voltage
– ICC
= supply current
• ICC
and VCC
are specified in the datasheet for
the integrated circuit (IC).
• For TTL devices, PS is significant.
• For CMOS devices, PS is very small (~0 W).
Fall 2010 ECE 331 - Digital System Design 6
Example: 74LS08
VCC
ICCH, ICCL
Fall 2010 ECE 331 - Digital System Design 7
Example: 74LS32
VCC
ICCH, ICCL
Fall 2010 ECE 331 - Digital System Design 8
Example: 74HC32
VCC
ICC
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Example: Static Power Consumption
IC VCC (max) ICCH (max) ICCL (max) PSH (max) PSL (max)
4.8 mA 25.2 mW
8.8 mA 46.2 mW
6.2 mA 32.55 mW
9.8 mA 51.45 mW
20 A 120 W
20 A 120 W74HC32 6.00 V
74LS32 5.25 V
74LS08 5.25 V
Fall 2010 ECE 331 - Digital System Design 10
Example: Static Power Consumption The static power consumption is a function of the
duty cycle. duty cycle – percentage of time in the high state
PS = PS_high * thigh + PS_low * tlow
where thigh = time in the high state
and tlow = time in the low state
Assume a 50% duty cycle PS = PS_high * 0.5 + PS_low * 0.5
Assume a 60% duty cycle PS = PS_high * 0.6 + PS_low * 0.4
Fall 2010 ECE 331 - Digital System Design 11
Example: Static Power Consumption
IC PSH (max) PSL (max) 50% 60%
25.2 mW
46.2 mW32.55 mW
51.45 mW120 W
120 W
74LS08
74LS32
74HC32
35.7 mW
42.0 mW
120 W
33.6 mW
40.11 mW
120 W
Fall 2010 ECE 331 - Digital System Design 12
Time Delay
Fall 2010 ECE 331 - Digital System Design 13
Time Delay
A standard logic gate does not respond to a change in its input(s) instantaneously.
There is, instead, a finite delay between a change in the input and a change in the output.
The propagation delay of a standard logic gate is defined for two cases:
tPLH = delay for output to change from low to high
tPHL = delay for output to change from high to low
Fall 2010 ECE 331 - Digital System Design 14
Time Delay
high-to-lowtransition
low-to-hightransition
tPHL tPLH
Fall 2010 ECE 331 - Digital System Design 15
Time Delay
The time delay (both tPLH and tPLH) for a logic gate is specified in its datasheet.
The time delay is also known as the gate delay propagation delay of the logic gate.
Fall 2010 ECE 331 - Digital System Design 16
Example: 74LS08
tPHL, tPLH
Fall 2010 ECE 331 - Digital System Design 17
Example: 74LS32
tPHL, tPLH
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Example: 74HC32
tPHL, tPLH
Fall 2010 ECE 331 - Digital System Design 19
Time Delay
The time delay of individual logic gates can be used to determine the overall propagation delay of a logic circuit.
The propagation delay of a logic circuit can be used to define
When the output of the logic circuit is valid. The maximum speed of the combinational logic circuit. The maximum frequency of the sequential logic circuit.
Fall 2010 ECE 331 - Digital System Design 20
Timing Analysis
A simple timing analysis can be performed on a logic circuit assuming that
only one input transitions at a time The time delay between the transition on the
input and the transition on the output can be determined as follows
identify the path between the input and output sum the gate delays of all gates in the path
Fall 2010 ECE 331 - Digital System Design 21
Timing Analysis However,
Some logic circuits have more than one path between an input and the output.
In some logic circuits, multiple inputs transition at the same time.
The simple timing analysis will not work. Instead, perform a more conservative timing
analysis using the Sum of Worst Cases (SWC) Analysis method
Fall 2010 ECE 331 - Digital System Design 22
Timing Analysis: SWC
Identify all input-output paths (i.e. delay paths) Using the datasheet, select the worst-case gate
delay for each logic gate. Select maximum of tPLH and tPHL
Calculate the worst-case delay for each path Sum the gate delays of the gates in the path
Select the worst case The maximum propagation delay for the circuit
Fall 2010 ECE 331 - Digital System Design 23
Timing Analysis: SWC
Example:
Using the SWC analysis method, determine the maximum propagation delay for the Exclusive-OR
(XOR) Logic Circuit.
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tPLH (ns) tPHL (ns)min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
Fall 2010 ECE 331 - Digital System Design 25
tPLH (ns) tPHL (ns)min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
tPD = 26.1 ns
Fall 2010 ECE 331 - Digital System Design 26
tPLH (ns) tPHL (ns)min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
tPD = 27.3 ns
A
B
F74F04
74LS04
74LS08
74F08
74F32
Fall 2010 ECE 331 - Digital System Design 27
tPLH (ns) tPHL (ns)min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
tPD = 32.1 ns
Fall 2010 ECE 331 - Digital System Design 28
tPLH (ns) tPHL (ns)min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
tPD = 12.3 ns
Fall 2010 ECE 331 - Digital System Design 29
Input Output Delay (ns)
A (1) F 26.1
A (2) F 27.3
B (1) F 32.1
B (2) F 12.3
Worst Case Propagation Delay = 32.1 ns
Example: SWC
Fall 2010 ECE 331 - Digital System Design 30
Transient Behavior
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When the input to a combinational logic circuit changes, unwanted switching transients may appear on the output.
These transients occur when different paths from input to output have different propagation delays.
Hazards
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Hazards
transient
Fall 2010 ECE 331 - Digital System Design 33
Static 1-Hazards
When analyzing combinational logic circuits for hazards we will consider the case where only one input changes at a time.
Under this condition, a static 1-hazard occurs when the input change causes one product term (in a SOP expression) to transition from 1 to 0 and another product term to transition from 0 to 1.
Both product terms can be transiently 0, resulting in the static 1-hazard.
Fall 2010 ECE 331 - Digital System Design 34
We can detect hazards in a two-level AND-OR circuit using the following procedure:
1. Write down the sum-of-products expression for the circuit.
2. Plot each term on the K-map and circle it.
3. If any two adjacent 1′s are not covered by the same circle, a 1-hazard exists for the transition between the two 1′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant.
Detecting Static 1-Hazards
Fall 2010 ECE 331 - Digital System Design 35
Detecting Static 1-Hazards
A = 1C = 1
B = 1 → 0 at 20ns gate delay = 10ns
Static 1-Hazard
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Removing Static 1-Hazards
redundant, but necessary to remove hazard
Fall 2010 ECE 331 - Digital System Design 37
Static 0-Hazards
Again, consider the case where only one input changes at a time
Under this condition, a static 0-hazard occurs when the input change causes one sum term (in a POS expression) to transition from 0 to 1 and another sum term to transition from 1 to 0.
Both sum terms can be transiently 1, resulting in the static 0-hazard.
Fall 2010 ECE 331 - Digital System Design 38
We can detect hazards in a two-level OR-AND circuit using the following procedure:
1. Write down the product-of-sums expression for the circuit.
2. Plot each sum term on the map and loop the zeros.
3. If any two adjacent 0′s are not covered by the same loop, a 0-hazard exists for the transition between the two 0′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant.
Detecting Static 0-Hazards
Fall 2010 ECE 331 - Digital System Design 39
Detecting Static 0-Hazards
A = 0B = 1D = 0C = 0 → 1 at 5ns
AND/OR delay = 5nsNOT delay = 3ns
Static 0-Hazard
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Removing Static 0-Hazards
How many redundant gates are necessary to remove the 0-hazards?
Fall 2010 ECE 331 - Digital System Design 41
Hazards
Exercise:
Design a hazard-free combinational logic circuit to implement the following logic function
F(A,B,C) = A'.C' + A.D + B.C.D'
Fall 2010 ECE 331 - Digital System Design 42
Hazards
Exercise:
Design a hazard-free combinational logic circuit to implement the following logic function
F(A,B,C) = (A'+C').(A+D).(B+C+D')
Fall 2010 ECE 331 - Digital System Design 43
Hazards
Two-level AND-OR circuits (SOP) cannot have Static 0-Hazards.
Why? Two-level OR-AND circuits (POS) cannot have
Static 1-Hazards. Why?
Fall 2010 ECE 331 - Digital System Design 44
Questions?
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