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ECE 331 – Digital System Design
Constraints in Logic Circuit Design
(Lecture #15)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Spring 2011 ECE 331 - Digital System Design 3
Power Consumption
• Each integrated circuit (IC) consumes power
• Power consumption can be divided into two
parts:
– Static power consumption (PS)
– Dynamic power consumption (PD)
• Total power consumption (PT) can then be
determined as
– PT = PS + PD
Spring 2011 ECE 331 - Digital System Design 4
Static Power Consumption
• PS = V
CC * I
CC
– VCC
= supply voltage
– ICC
= supply current
• ICC
and VCC
are specified in the datasheet for
the integrated circuit (IC).
• For TTL devices, PS is significant.
• For CMOS devices, PS is very small (~0 W).
Spring 2011 ECE 331 - Digital System Design 8
Example: Static Power Consumption
IC VCC (max) ICCH (max) ICCL (max) PSH (max) PSL (max)
74LS08 5.25 V4.8 mA 25.2 mW
8.8 mA 46.2 mW
74LS32 5.25 V6.2 mA 32.55 mW
9.8 mA 51.45 mW
74HC32 6.00 V20 µA 120 µW
20 µA 120 µW
Spring 2011 ECE 331 - Digital System Design 9
Example: Static Power Consumption● The static power consumption is a function of the
duty cycle.
– duty cycle – percentage of time in the high state
● PS = PS_high * thigh + PS_low * tlow
– where thigh = time in the high state
– and tlow = time in the low state
● Assume a 50% duty cycle
– PS = PS_high * 0.5 + PS_low * 0.5
● Assume a 60% duty cycle
– PS = PS_high * 0.6 + PS_low * 0.4
Spring 2011 ECE 331 - Digital System Design 10
Example: Static Power Consumption
IC PSH (max) PSL (max) 50% 60%
74LS0825.2 mW
35.7 mW 33.6 mW46.2 mW
74LS3232.55 mW
42.0 mW 40.11 mW51.45 mW
74HC32120 µW
120 µW 120 µW120 µW
Fall 2010 ECE 331 - Digital System Design 11
Dynamic Power Consumption
● For TTL devices, PD is negligible compared to PS.
– Assume PD = 0
● For CMOS devices, PD dominates PT.
– PD >> PS
● PD in CMOS circuits arises from the movement of
charge into and out of the device capacitance.
Fall 2010 ECE 331 - Digital System Design 12
Dynamic Power Consumption
● In CMOS devices, charge is stored in the
– CPD = power dissipation capacitance (internal)
– CL = capacitance of the load and wires
(external)
● These capacitors are in parallel
– CT = CPD + CL
● The stored charge (on these capacitors) is
– QT = CT * VDD = (CPD + CL) * VDD
Fall 2010 ECE 331 - Digital System Design 13
Dynamic Power Consumption
● The charge moves into and out of the capacitors on every transition of the output.
– Low → High
– High → Low
● Current = movement of charge
– IAVG = (CPD + CL) * VDD * fT
● Where fT = output frequency
● PD = IAVG * VDD = (CPD + CL) * V2
DD * fT
Spring 2011 ECE 331 - Digital System Design 15
Example: Dynamic Power Consumption
● From the data sheet for the 74HC00
– VDD = 6V, CPD = 20 pF, CL = 50 pF
● PD = (20 pF + 50 pF) * (6V)2 * fT
fT (Hz) PD (W)
1 K 2.5 µ
1 M 2.52 m
100 M 252 m
Fall 2010 ECE 331 - Digital System Design 17
Example: Total Power Consumption
● For the 74HC00, PS is determined as follows
– VDD = 6V
– IDD = 20 µA
– PS = VDD * IDD = 6V * 10 µA = 60 µW (~ 0 W )
● The PT is then determined from
– PT = PS + PD
– where PD is a function of fT
Fall 2010 ECE 331 - Digital System Design 18
Total Power Consumption
● Compare PT for 74xx00 (Quad 2-input NAND):
0 Hz 1 MHz 100 MHz
LS (TTL) 15.8 mW 15.8 mW 15.8 mW
HC (CMOS) 60 µW 2.58 mW 250 mW
Fall 2010 ECE 331 - Digital System Design 19
Total Power Consumption
● Compare TTL and CMOS:
TTL CMOS
PS VCC * ICC VDD * IDD
PD ~ 0 W (CPD + CL) * (VDD)2 * fT
Spring 2011 ECE 331 - Digital System Design 21
Time Delay
● A standard logic gate does not respond to a change in its input(s) instantaneously.
● There is, instead, a finite delay between a change in the input and a change in the output.
● The propagation delay of a standard logic gate is specified in its data sheet.
– tPLH = low-to-high propagation delay
– tPHL = high-to-low propagation delay
Spring 2011 ECE 331 - Digital System Design 22
Time Delay
● The time delay of individual logic gates can be used to determine the overall propagation delay of a logic circuit.
● The propagation delay of a logic circuit can be used to define
– When the output of the logic circuit is valid.
– The maximum speed of the combinational logic circuit.
– The maximum frequency of the sequential logic circuit.
Spring 2011 ECE 331 - Digital System Design 23
Timing Analysis
● A simple timing analysis can be performed on a logic circuit assuming that
– only one input transitions at a time
● The time delay between the transition on the input and the transition on the output can be determined as follows
– identify the path between the input and output
– sum the gate delays of all gates in the path
Spring 2011 ECE 331 - Digital System Design 24
Timing Analysis
● However,
– Some logic circuits have more than one path between an input and the output.
– In some logic circuits, multiple inputs transition at the same time.
● The simple timing analysis will not work.
● Instead, perform a more conservative timing analysis using the
– Sum of Worst Cases (SWC) Analysis method
Spring 2011 ECE 331 - Digital System Design 25
Timing Analysis: SWC
● Identify all input-output paths (i.e. delay paths)
● Using the datasheet, select the worst-case gate delay for each logic gate.
– Select maximum of tPLH and tPHL
● Calculate the worst-case delay for each path
– Sum the gate delays of the gates in the path
● Select the worst case
– The maximum propagation delay for the circuit
Spring 2011 ECE 331 - Digital System Design 26
Timing Analysis: SWC
Example:
Using the SWC analysis method, determine the maximum propagation delay for the Exclusive-OR
(XOR) Logic Circuit.
Spring 2011 ECE 331 - Digital System Design 27
tPLH (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
Spring 2011 ECE 331 - Digital System Design 28
tPLH (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
tPD = 26.1 ns
Spring 2011 ECE 331 - Digital System Design 29
tPLH (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
tPD = 27.3 ns
A
B
F74F04
74LS04
74LS08
74F08
74F32
Spring 2011 ECE 331 - Digital System Design 30
tPLH (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
tPD = 32.1 ns
Spring 2011 ECE 331 - Digital System Design 31
tPLH (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
Example: SWC
A
B
F74F04
74LS04
74LS08
74F08
74F32
tPD = 12.3 ns
Spring 2011 ECE 331 - Digital System Design 32
Input Output Delay (ns)
A (1) F 26.1
A (2) F 27.3
B (1) F 32.1
B (2) F 12.3
Worst Case Propagation Delay = 32.1 ns
Example: SWC
Spring 2011 ECE 331 - Digital System Design 34
Hazards
● When the input to a combinational logic circuit changes, unwanted switching transients may appear on the output.
● These transients occur when different paths from input to output have different propagation delays.
Spring 2011 ECE 331 - Digital System Design 36
Static 1-Hazards
● When analyzing combinational logic circuits for hazards we will consider the case where only one input changes at a time.
● Under this condition, a static 1-hazard occurs when the input change causes one product term (in a SOP expression) to transition from 1 to 0 and another product term to transition from 0 to 1.
● Both product terms can be transiently 0, resulting in the static 1-hazard.
Spring 2011 ECE 331 - Digital System Design 37
We can detect hazards in a two-level AND-OR circuit using
the following procedure:
1. Write down the sum-of-products expression for the circuit.
2. Plot each term on the K-map and circle it.
3. If any two adjacent 1′s are not covered by the same circle, a 1-hazard
exists for the transition between the two 1′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1
variables are held constant.
Detecting Static 1-Hazards
Spring 2011 ECE 331 - Digital System Design 38
Detecting Static 1-Hazards
A = 1C = 1
B = 1 → 0 at 20ns gate delay = 10ns
Static 1-Hazard
Spring 2011 ECE 331 - Digital System Design 39
Removing Static 1-Hazards
redundant, but necessary
to remove hazard
Spring 2011 ECE 331 - Digital System Design 40
Static 0-Hazards
● Again, consider the case where only one input changes at a time.
● Under this condition, a static 0-hazard occurs when the input change causes one sum term (in a POS expression) to transition from 0 to 1 and another sum term to transition from 1 to 0.
● Both sum terms can be transiently 1, resulting in the static 0-hazard.
Spring 2011 ECE 331 - Digital System Design 41
We can detect hazards in a two-level OR-AND circuit using
the following procedure:
1. Write down the product-of-sums expression for the circuit.
2. Plot each sum term on the map and loop the zeros.
3. If any two adjacent 0′s are not covered by the same loop, a 0-hazard
exists for the transition between the two 0′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1
variables are held constant.
Detecting Static 0-Hazards
Spring 2011 ECE 331 - Digital System Design 42
Detecting Static 0-Hazards
A = 0B = 1
D = 0
C = 0 → 1 at 5ns
AND/OR delay = 5nsNOT delay = 3ns
Static 0-Hazard
Spring 2011 ECE 331 - Digital System Design 43
Removing Static 0-Hazards
How many redundant gates are necessary to remove the 0-hazards?
Spring 2011 ECE 331 - Digital System Design 44
Hazards
Exercise:
Design a hazard-free combinational logic circuit to implement the following logic function
F(A,B,C,D) = A'.C' + A.D + B.C.D'
Spring 2011 ECE 331 - Digital System Design 45
Hazards
Exercise:
Design a hazard-free combinational logic circuit to implement the following logic function
F(A,B,C,D) = (A'+C').(A+D).(B+C+D')
Spring 2011 ECE 331 - Digital System Design 46
Hazards
● Two-level AND-OR circuits (SOP) cannot have Static 0-Hazards.
● Two-level OR-AND circuits (POS) cannot have Static 1-Hazards.
Why?
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