View
218
Download
1
Category
Tags:
Preview:
Citation preview
ECE 2110: Introduction to Digital Systems
Course Review
2
Digital Design Basics
Analog vs DigitalWhy we need digital?
Reproducibility, economy, programmability…
Digital Devices Gates, FFs Combinational, sequential circuits
3
Integrated Circuits (IC)
A collection of one or more gates fabricated on a single silicon chip. Wafer, die
Small-scale integration (SSI): 1-20 DIP: dual in-line-pin package Pin diagram, pinout
MSI: 20-200 gates LSI: 200-200,000
VLSI: >100,000, 50million (1999)
4
Binary Representation
The basis of all digital data is binary representation. Binary - means ‘two’
1, 0 True, False Hot, Cold On, Off
We must be able to handle more than just values for real world problems 1, 0, 56 True, False, Maybe Hot, Cold, Warm, Cool On, Off, Leaky
5
Unsigned numbers
N binary digits (N bits) can represent unsigned integers from 0 to 2N-1.
Conversions: Hex <----->binary Octal <-----> binary
(padded with zero) Any base <----->decimal
Operations (binary): addition/subtraction
6
Representation of Negative Numbers
Signed-Magnitude Representation: Negates a number by changing its sign.
Complement Number Systems: negates a number by taking its complement. Diminished Radix-Complement Representation
One’s-Complement Radix-Complement Representation
Two’s-Complement
7
NOTE:
Fix number of digits
SM, 1’s complement, 2’s complement may be different for NEGATIVE numbers, but
for positive numbers, the representations in SM, 1’s complement, 2’s complement are the SAME, equals to the unsigned binary representation.
8
Ranges (N bits)
1’s complement can represent the signed integers
-2(N-1) - 1 to + 2(N-1) - 1
unsigned binary can represent unsigned integers from 0 to 2N-1.
SM can represent the signed integers
-2(N-1) - 1 to + 2(N-1) - 1
2’s complement can represent the signed integers
-2(N-1) to + 2(N-1) - 1
9
Sign extension
For unsigned binary, Just add zeros to the left.
For signed binary (SM,1’s,2’s complement…): Take whatever the SIGN BIT is, and extend
it to the left.
10
Conversions for signed numbers
Hex--->signed decimal Given a Hex number, and you are told to convert to a signed integer (either as
signed magnitude, 1s complement, 2s complement) Step 1: Determine the sign Step 2: determine magnitude Step 3: combine sign and magnitude
Signed decimal ---->hex Step 1: Know what format you are converting to!!! Ignore the sign, convert the magnitude of the number to binary. Step 3 (positive decimal number): If the decimal number was positive,
then you are finished no matter what the format is! Step 3 (negative decimal number): more work need to do.
11
signed addition/subtraction
Two’s-complement Addition rules Subtraction rules
Overflow: Out of range Detecting unsigned overflow (carry out of MSB) Detecting 2’s complement overflow
12
Detecting Two’s Complement Overflow
Two’s complement overflow occurs if:
Add two POSITIVE numbers and get a NEGATIVE result Add two NEGATIVE numbers and get a POSITIVE result
We CANNOT get two’s complement overflow if I add a NEGATIVE and a POSITIVE number together.
The Carry out of the Most Significant Bit means nothing if the numbers are two’s complement numbers.
13
Codes
Code: A set of n-bit strings in which different bit strings represent different numbers or other things.
Code word: a particular combination of n-bit values N-bit strings at most contain 2n valid code words.
To represent 10 decimal digits, at least need 4 bits. Excessive ways to choose ten 4-bit words. Some
common codes: BCD: Binary-coded decimal, also known as 8421 code 2421 -8421
Codes can be used to represent numerical numbers, nonnumeric texts, events/actions/states/conditions
14
Switching Algebra
Variables, expressions, equationsAxioms (A1-A5 pairs)Theorems
Single variable 2- or 3- variable N-variables
Prime, complement, logic multiplication/addition, precedence
15
How to prove a theorem?
Perfect induction (1,2,3-variable)
Finite Induction (n-variable)
16
Duality
Swap 0 & 1, AND & OR Result: Theorems still true
Principle of Duality Any theorem or identity in switching algebra remains
true if 0 and 1 are swapped and • and + are swapped throughout.
Fully parenthesized before taking its duality
17
Representations for a combinational logic function
Truth tableAlgebraic sum of minterms (canonical
sum)Minterm listAlgebraic product of maxterms (canonical
product)Maxterm list
18
Combinational-circuit analysis
Obtain a formal representation of a given circuit Truth table: axioms, exhaustive Logic expression: algebraic approach
19
Combinational circuit synthesis
Description--->combinational logic circuit. Description:
Word description of a problem using English-language connectives
Write corresponding logic expression/truth table Manipulate the expression if necessary. Build a circuit from the expression.
20
Minimization
Logic Function minimization : Simplifying the logic function to reduce the number and size of gates.
Minimization methods:
1- Algebraic simplification: Using theorems T9,T9’, T10,T10’
2- Karnaugh map(SOP, POS, multiple-outputs, Don’t Cares)
21
Simplifying SOP:
Draw K-map Find prime implicants (circle largest rectangular sets
of 1s: …16,8,4,2,1) Find distinguished 1-cell Determine essential prime implicants if available Select all essential prime implicants and the minimal
set of the remaining prime implicants that cover the remaining 1’s.
22
Simplifying POS
Products-Of-Sums(POS) minimization Duality: circle 0s on the K-map F=(F’)’
Draw a K-map for F’ Simplifying SOP for F’ Get POS for F using DeMorgan theorems
repeatedly:F=(F’)’
23
Other minimization issues
Don’t care conditions d Since the output function for those minterms (maxterms)
is not specified, those minterms (maxterms) could be combined with the adjacent 1 cells(0-cells) to get a more simplified sum-of-products (product-of-sums) expression.
d cells are only combined when we have to.
Multiple-outputs Term sharing can reduce costs
24
Documentation Standards
Documentation of a digital system should provide the necessary information for building, testing ,operating , and maintaining the system.
Generally, documentation include:1) A Specification describes what the circuit is supposed to do.2) A block diagram showing the inputs, outputs, the main building
blocks ( modules) of the system and how they are connected.3) A schematic diagram showing all the components, their types, and
all interconnections. 4) A timing diagram showing the logic signals as a function of time.5) A Circuit description explaining of the operation of the logic circuit.
25
Block Diagram
A block diagram should show all inputs and outputs , the building blocks and their function names , and the data flow paths ( the logic signals).- The internal details of each block should not be shown.- Related logic signals are combined together and drawn with a double or heavy line, known as a bus
Example: Min/Max Circuit
Comparator
Mux
Mux
Mux
XY
Z
MIN/MAX
X>Y
max(X,Y)
min(X,Y)
A bus is a collection of 2 or more related signal lines.
26
Schematic Diagram
Details of component inputs, outputs, and interconnections
Reference designatorsPin numbersGate symbolsSignal names and active levelsBubble-to-Bubble Logic DesignLayouts
27
DeMorgan equivalent symbols
Which symbol to use?
Answer depends on signal names and active levels.
28
Active Levels
Each signal name should have an active-level associated with it. A signal is active-high if it performs the named action or denotes the named condition when it’s HIGH or 1. A signal is active-low if it performs the named action or denotes the named condition when it’s LOW or 0.
The signal is asserted when it is in its active level and negated ( or deasserted ) when its not in its active level.
Different naming conventions for active levels available.
29
Bubble-to-Bubble Logic Design Rules
- The active level of the output signal of a logic device should match the active level of the device’s output pin.Active-low if the device symbol has an inversion bubble, active-high if not.
- If the active level of an input signal is the same as that of the device’s input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is asserted.Most common case.
- If the active level of an input signal is the opposite of that of the input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is negated. Should be avoided.
ERROR
READY
ERROR
READY_L
REQUEST
ENABLE_L
REQUEST
ENABLE
HALT_LERROR
OVERFLOW
ERRORFAIL_L
OVERFLOW_L
30
Timing Diagrams
A timing diagram illustrates the logical behavior of signals as a function of time.
Causality: which input transitions cause which output transitions.
Different through a circuit paths may have different delays. A signal timing diagram may contain many different delay
specifications. Delay depends on
- Internal circuit structure- Logic Family type- Source Voltage- Temperature
31
Propagation Delay
The delay time between input transitions and the output transitions due to the propagation delay of the the logic gates.
tp of a signal depends on the signal path inside the logic circuit For a logic gate tpLH may not equal tpHL
tp is specified in the manufacturer data sheets of the IC’s Example :
-The time delay for 74x00 in nanosecods for three Logic Families: Typical Maximum tpLH tpHL tpLH tpHL
74LS00 9 10 15 1574HCT00 11 11 35 35 74ACT00 5.5 5.5 9.0 9.0
To find tp for a signal, add the propagation delays of all gates along the path of the signal
32
Timing analysis
Study logical behavior of SSI/MSI devicesDelay info for some SSI and MSI devices
(Tables 6-2, 6-3)Worst-case delay:
Maximum of tpLH and tpHL for each component
Sum of the worst-case delays through the individual components, independent of the transition direction and other conditions.
33
Combinational Building Blocks
1-Decoders : Binary Decoders, Implementing Logic Functions
2-Encoders : Binary Encoder, Encoder applications
3- MultiplexersMUX operation, Single outputs MUX, Multiple output MUX, Implementing Logic Functions
34
4- DemultiplexersMUX/DMUX operation, Using Decoders as
Demultiplexers. 5- XOR Gates
Logic Symbols, Equivalent Symbols, Parity circuits using XOR gate,
6-Adders/Subtractors : Half Adder, Full Adder, Ripple Adder
7- Arithmetic Logic Units
35
Sequential Systems
A combinational system is a system whose outputs depends only upon its current inputs.
A sequential system is a system whose output depends on current input and past history of inputs.
36
Describing Sequential Circuits
State table For each current-state, specify next-states as
function of inputs For each current-state, specify outputs as
function of inputs
State diagram Graphical version of state table
37
Clock signals
Very important with most sequential circuits State variables change state at clock edge.
38
Sequential Building Blocks
Bistable elements Latches
S-R D
FFs D FF J-K FF T FF T with En
39
State Machine Structure
State memory: n FFs to store current states. All FFs are connected to a common clock signal.
Next-state logic: determine the next state when state changes occur;
Output logic: determines the output as a function of current state and input
Moore machine
40
Summary: how to analyze a clocked synchronous state machine?
1) Determine the excitation equations for the FF control inputs;2) Substitute the excitation equations into the FF characteristic
equations to obtain transition equations;3) Use the transition equations to construct a transition table;4) Determine the output equations;5) Add output values to the transition table for each state (Moore)
to create a transition/output table;6) Name the states and substitute state names for state-variable
combinations in the transition/output table to obtain state/output table;
7) Draw a sate diagram corresponding to the state/output table.
41
Summary: how to design a clocked synchronous state machine?
1) Draw a state diagram corresponding to the problem statement2) Derive state table from state diagram.3) Choose a set of state variables and assign state variable
combinations to named states.4) Substitute the state variable combinations into state table to
derive the transition table.5) Choose a Flip-Flop (usually D FF). Note its characteristic
equations.6) Determine the excitation table by replacing the next state
variables by their excitation.7) Derive excitation equations from the excitation table. Use K-
Maps to minimize the excitation equations. 8) Derive the output equations.9) Draw logic diagram.
Recommended