Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization K.Yuan,...

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

K.Yuan, J.Yang and D.Pan

ECE Dept. Univ. of Texas at Austin

ISPD 2009

Outline

Introduction Preliminaries and Motivation Problem Formulation Algorithm

Basic ILP Formulation Speed-Up Techniques Solution Mergence

Experimental Result Conclusion

Introduction

As the minimum feature size decreases, semiconductor industry is facing the limitation of patterning sub-32nm.

Double patterning lithography (DPL) is considered as a most likely solution for 32nm/22nm technology.

In DPL, a single layout is decomposed into two masks and manufactured through two exposure steps.

Introduction

As a benefit, the pitch size is doubled, which enhances the resolution.

Introduction

Decomposition is a process that assigns opposite colors if the distance between two features is less than the minimum coloring spacing.

A feature may be split into two parts and colored differently to resolve the conflicts, which generates stitches.

Stitches cause yield loss due to overlay error and they also increase manufacturing cost.

Preliminaries and Motivation

Layout Decomposition Considerations Coloring Conflict: If the distance between two separate features i

n the same mask is less than mincs, they should be assigned to different colors. Otherwise, there will be a coloring conflict.

Preliminaries and Motivation

Layout Decomposition Considerations Splitting Stitch: The stitch exists when two touched features are

assigned to different masks.

Preliminaries and Motivation

Simultaneous Optimization

Preliminaries and Motivation

Simultaneous Optimization

Problem Formulation

Different stitch candidates can lead to different solution qualities.

Problem Formulation

The difficulty of predicting where the splitting is needed.

Problem Formulation

The difficulty of predicting where the splitting is needed.

Problem Formulation

Grid Layout Model Map the whole layout into grids. Each grid is either empty or fully occupied by the pattern. Each occupied grid will be assigned one color. Minimum coloring spacing mincs is taken as two-grid size.

Problem Formulation

Terms Occupied grid (OG): The grid filled by the layout. Blocking path (BP): Given two OG1 and OG2, a BP is a path whe

n It is fully composed of the OGs and connects OG1 and OG2. OG1 and OG2 are touching its two ending grids, respectively. This path is within the bounding box of OG1 and OG2.

Problem Formulation

Terms Potential conflict grid pair (PCGP) and potential stitch grid pair (PSGP): Given two OG1 and OG2, If the distance between OG1 and OG2 is less than mincs and the two

grids are not touching, they form a PCGP. If OG1 and OG2 are touching, they form a PSGP.

Stitch grid pair (SGP): If the grids of a PSGP are assigned different colors, it is a SGP.

Conflict grid pair (CGP): If a PCGP is in the identical color, and there is no BP connecting them in the same mask, it is a CGP.

Problem Formulation

Problem Formulation

Problem Formulation

Problem formulation: Given a grid layout, color it into two parts (GRAY and BL

ACK). The primary objective is to minimize the number of CGPs and the second objective is to minimize the number of SGPs.

Algorithm

The overall layout decomposition flow.

Algorithm

Basic ILP Formulation

Algorithm

Basic ILP Formulation

(1) is to minimize the weighted summation of SGPs and CGPs. (2) and (3) are used to identify SGP from PSGP. (4)-(9) is to determine whether a PCGP forms a CGP. (8) and (9) evaluates the conditions for CGP.

Algorithm

Speed-Up techniques Independent component computation

Many isolated occupied grid clusters, there are no PSGPs or PCGPs formed between them.

Break down the whole design into several independent components. Apply basic ILP formulation for each one.

Algorithm

Speed-Up techniques Layout partition

Divide a big component into several small connected partitions and perform ILP approach for each one.

Different from the independent component computation, there will be some PSGPs/PCGPs between different partitions.

Algorithm

Solution Mergence After solving the solution for each component/partition, need to

merge the coloring assignment as a whole.

Algorithm

Solution Mergence SGPe/CGPe: external conflicts/stitiches crossing the b

oundary of different partitions.

Coloring flip optimization: Given a number of partitions and their coloring solutions for one independent component, choose the best flipping scheme to minimize total cost of SGPe and CGPe.

Algorithm

Solution Mergence Coloring flip optimization

Experimental Result

Experimental Result

Experimental Result

Experimental Result

Experimental Result

Conclusion

This paper has developed a double patterning aware layout decomposition flow for simultaneous conflict and stitch minimization.

The approach is featured by grid layout model and integer linear programming.