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Table of Contents
Design MethodologiesOverview of IC Design FlowHardware Description LanguagesBrief History of HDLs
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Ad-hoc DesignSmall Scale Designs
Come up with a block diagramPlace chips on boardWire parts and componentsHope or Pray it works
Large Scale DesignsPartition DesignDevelop LibraryConfigure DesignTest Partial DesignDevelop More LibrariesConfigure More Designs. . .Complete Design
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Why Structured Design?
Over a million-transistor designs cannot be done easily
Today’s designs require better toolsToday’s designs require better planningToday’s designs require better strategy
How to manageStep-by-step designUse of SimulationUse of Synthesis
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Design Methodologies (cont.)
Top-DownRefine Specification successivelyDecompose each component into small componentsLowest-level primitive componentsOver-sold methodology - only works with plenty of experience
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Design Methodologies (cont.)
Bottom-UpBuild-up from primitive componentsCombined to form more complex componentsRisk wrong interpretation of specifications
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Design Methodologies (cont.)
MixedMostly top-down, but also bits of bottom-upReality: need to know both top level and bottom level constraints
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Overview of IC Design
From Concept to Silicon
Verification must bedone at each phase
Concept
Algorithm Design
Architecture Design
Logic/Circuit Design
Physical Design
Tape-out
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Overview of IC Design (cont.)
ConceptNovel Idea or Product Concept
Algorithm DesignProving IdeaBehavior AnalysisAlgorithm Optimization & Transformations
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Overview of IC Design (cont.)Architecture Design
Design of Hardware ComponentsOptimization for Minimum Resource
Logic/Circuit DesignDesign of Hardware ComponentsTradeoffs among Area/Delay/PowerFurther Improvements from logic-level to circuit level
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Overview of IC Design (cont.)
Physical DesignTarget to a Foundry ProcessLayout according to Routing LayersRC Model for TransistorsInitial Floorplan
Estimate Die SizeEstimate Routing Complexity
Finial Floorplan
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Overview of IC Design (cont.)
Tape-outFabrication Period
Gate ArrayRouting Layers and Contacts are required
Full-Custom or Cell-BasedAll Masks must be designed
A lot of test after manufacturing is needed before design is ready for market
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Overview of IC Design (cont.)Verification
Validation of Design in each PhaseFormalSimulation
Equivalence Checking between two phasesPhysical Design Verification
DRC: Design Rule CheckERC: Electrical Rule CheckLVS: Layout vs. Schematic
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Hardware Description Languages (HDLs)
Describe Hardware at different levels of abstractionStructural
Netlist of modules (hierarchical)Textual replacement of Schematic
Behavioral/FunctionalDescribe what module does, not howUse Synthesis to generate Hardware
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Why Using HDLs?
Very difficult to design directly on hardwareExploring different design options
EasierCheaper
Lower time and cost than prototypingCAD support from concept to silicon
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Key Features of HDLs
HDLs have high-level programming language constructsHDLs allow designers to describe their designs at different levels of abstractionHDLs allow designers to describe functionality as well as timingHDLs are concurrent languages in nature
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CDL
Computer Design LanguageDeveloped in 1965
Simulator in 1975Features:
Some high-level statements, conditionSimple logical and arithmetic operationsAcademic language (not industrial)Data-flow level (no hierarchy support)
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ISPS
Instruction Set Processor SpecificationFirst Idea in 1971
ISPL in 1976ISPS in 1981
Single level of abstractionUpper than data-flowProcessor instruction set
No hierarchy support
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AHPL
A Hardware Programming LanguageThree versions:
AHPL-I: 1970AHPL-II: 1978AHPL-III: 1979
Features:Data-flow and structural levelFull EDA tool supportUnfamiliar syntax
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VHDL
VHSIC HDL: Very High Speed Integrated Circuit Hardware Description LanguageInitiated by DARPA (research center of DoD) in a workshop in 1981DARPA documentation released in 1983VHDL 7.2 released in 1985
ITAR restrictions were lifted from VHDL
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VHDL (cont.)
IEEE Standard in 1987IEEE Std-1076-1987
ANSI Standard in 1988Added Support for RTL Design
VITAL: VHDL Initiative Towards ASIC Library
Revised version in 1993IEEE Std-1076-1993
Final review added mixed-signal support to VHDL in 2001 -> VHDL-AMS
IEEE Std-1076.1-2001
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Verilog
Verifying LogicPhil Moorby from Gateway Design Automation in 1984 to 1987
Absorbed by CadenceVerilog-XL simulator from GDA in 1986Synopsis Synthesis Tool in 1988In 1990 became open language
OVI: Open Verilog International
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Verilog (cont.)
IEEE Standard in 1995IEEE Std-1364-1995
Last revision in 2001IEEE Std-1364-2001
Ongoing work for addingMixed-signal constructs: Verilog-AMSSystem-level constructs: SystemVerilog
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VHDL vs. Verilog
All abstraction levelsDesigned for documentationADA based constructsNO PLI (Programming Language Interface)
All Abstraction LevelsDesigned for hardware designC and ADA based constructsPowerful PLI
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VHDL vs. Verilog (cont.)
Complex GrammarHard to learn for beginnersDescribe a system (everything)Lots of data typesHigh-level data types
PointerAlias
Easy LanguageEasy to learn for beginnersDescribe digital systemsFew data typesHardware related types
Wireregister
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VHDL vs. Verilog (cont.)
User-defined package and libraryReuse code from packageFull design parameterizationMore easier to handle large designs
No user-defined packagesReuse using includeSimple parameterizationNo language construct for design file handling
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