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Digital Integrated Circuits - week nine -. Gheorghe M. Ş tefan http://arh.pub.ro/gstefan/ - 2014 -. Veitch-Karnaugh diagrams. m 0 = a’b’c’d ’ Are based on the minimal Hamming distance m 1 = a’b’c’d between adjacent cells m 2 = a’b’cd ’ - PowerPoint PPT Presentation
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Gheorghe M. Ştefan http://arh.pub.ro/gstefan/
- 2014 -
Veitch-Karnaugh diagramsm0 = a’b’c’d’ Are based on the minimal Hamming distance
m1 = a’b’c’d between adjacent cells
m2 = a’b’cd’
m3 = a’b’cd
m4 = a’bc’d’
m5 = a’bc’d
m6 = a’bcd’
m7 = a’bcd
m8 = ab’c’d’
m9 = ab’c’d
. . .m15 = abcd
Veitch version2014 Digital Integrated Circuits - week nine 2
2014 Digital Integrated Circuits - week nine 3
Karnaugh version
2014 Digital Integrated Circuits - week nine 4
Minimizing logic functionssmallest number, of rectangular surfaces of 1’s, with maximal area,containing 2i 1’s, and including all 1’s
2014 Digital Integrated Circuits - week nine 5
“don’t care”s
2014 Digital Integrated Circuits - week nine 6
a’b +a’c b + c
V-K’s with included functionsIs a two-step process:1.Only 1’s2.1’s become “don’t’ care”s
(bc’d + a’bc’ + b’c) + (acde + c’de’)
2014 Digital Integrated Circuits - week nine 7
Transition diagrams
2014 Digital Integrated Circuits - week nine 8
Moore version
2014 Digital Integrated Circuits - week nine 9
2014 Digital Integrated Circuits - week nine 10
Mealy version
2014 Digital Integrated Circuits - week nine 11
Verilog modulesImmediate Moore version for ‘bb
detector’
2014 Digital Integrated Circuits - week nine 12
State transition function:
2014 Digital Integrated Circuits - week nine 13
Output transition function:
For the delayed version: always @(posedge clock)
case(state)
init_state : out <= no;
. . .
2014 Digital Integrated Circuits - week nine 14
For the immediate Mealy version of ‘bb detector’ only the output function is different:
For the delayed version the change is similar as for
Moore version 2014 Digital Integrated Circuits - week nine 15
Automata are complex circuitsThe number of lines in the Verilog description:
Are equal with the number of states for the behavioral descriptions
Are equal with the number of gates used for the structural descriptions
The transition diagrams have the size in O(|Q| log |Q|)
Because they are complex we must keep them small
2014 Digital Integrated Circuits - week nine 16
State coding
2014 Digital Integrated Circuits - week nine 17
First coding
Second coding
First version: Second version:
2014 Digital Integrated Circuits - week nine 18
Coding stylesMinimal variation encoding:
successive states are coded with minimal Hamming distance
Reduced dependency encoding:minimal Hamming distance for states
preceded by the same stateIncremental encoding:
whenever possible successive state are coded by incremented values
One-hot state encoding: one bit per state
2014 Digital Integrated Circuits - week nine 19
Minimal variation encoding
2014 Digital Integrated Circuits - week nine 20
Reduced dependency encoding
2014 Digital Integrated Circuits - week nine 21
Reduced dependency on both, X0 and X1 has no solution
Parasitic effects in automata
Automata with asynchronous inputs
Automata with asynchronous outputsHazard generated by asynchronous inputs
Propagation hazardDynamic hazard2014 Digital Integrated Circuits - week nine 22
Automata with asynchronous inputs
If the input variable switches asynchronously the input of the state register can vary in the prohibited time – tsu + t+ +th
No problems if only one bit switches:00 -> 01 => 00 -> 01 or 00 -> 00
Big problems if more than one bit switch:01 -> 10 => 01 -> 10 or 01 -> 00 or 01 -> 11 or 01 -> 01
The automaton evolves wrongly in the state space
2014 Digital Integrated Circuits - week nine 23
The solution: reduced dependency state coding
What can be done if there are state transitions depending on two or more asynchronous input variable ?
2014 Digital Integrated Circuits - week nine 24
Asynchronous outputs:hazard due to asynchronous inputs
2014 Digital Integrated Circuits - week nine 25
2014 Digital Integrated Circuits - week nine 26
Asynchronous outputs:propagation hazard
2014 Digital Integrated Circuits - week nine 27
Avoiding propagation hazard Partial protection Full
protection
2014 Digital Integrated Circuits - week nine 28
Dynamic hazard
Due to many-level combinational circuits (ex: carry propagation)
2014 Digital Integrated Circuits - week nine 29
Fundamental limitsThe asynchronous input bits can be considered only
independently in distinct states Immediate Mealy automata with asynchronous
inputs can not have actual implementations (unpredictable outputs)
Delayed Mealy automata with asynchronous inputs can not have actual implementations (the state and outputs could evolve uncorrelated)
Hazard free Moore with asynchronous inputs have no actual solution (state must be encoded simultaneously with minimal variation and reduced dependency)
2014 Digital Integrated Circuits - week nine 30
Home work 9 Problem 1:
2014 Digital Integrated Circuits - week nine 31
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