Digital Integrated Circuits© Prentice Hall 1995 Devices The MOS Transistor

Digital Integrated Circuits © Prentice Hall 1995DevicesDevices

The MOS Transistor

p-substrate

Field-Oxyde

(SiO2)

p+ stopper

Polysilicon

Gate Oxyde

DrainSource

Bulk Contact

CROSS-SECTION of NMOS Transistor

Cross-Section of CMOS Technology

MOS transistors Types and Symbols

NMOS Enhancement NMOS

Depletion

Enhancement

NMOS withBulk Contact

Threshold Voltage: Concept

p-substrate

Depletion

Region

n-channel

Current-Voltage Relations

p-substrate

V(x) +–

MOS transistor and its bias conditions

Current-Voltage Relations

Transistor in Saturation

VDS > VGS - VT

VGS - VT+-

I-V Relation

0.0 1.0 2.0 3.0 4.0 5.0

VDS (V)

0.0 1.0 2.0 3.0VGS (V)

SubthresholdCurrent

Triode Saturation

VGS = 5V

VGS = 3V

VGS = 4V

VGS = 2V

VGS = 1V

(a) ID as a function of VDS (b) ID as a function of VGS

(for VDS = 5V).

VDS = VGS-VT

NMOS Enhancement Transistor: W = 100 m, L = 20 m

A model for manual analysis

The Sub-Micron MOS Transistor

• Threshold Variations

• Parasitic Resistances

• Velocity Sauturation and Mobility Degradation

• Subthreshold Conduction

• Latchup

Threshold Variations

Long-channel threshold Low VDS threshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

Parasitic Resistances

Draincontact

Polysilicon gate

VGS,eff

Velocity Saturation (1)

EV/m)Esat

sat = 107

Constant mobility (slope = )

constant velocity

EtV/m)

(b) Mobility degradation(a) Velocity saturation

Velocity Saturation (2)

VDS (V)

VGS = 5

VGS = 4

VGS = 3

VGS = 2

VGS = 1

0.0 1.0 2.0 3.0 4.0 5.0

(a) ID as a function of VDS (b) ID as a function of VGS(for VDS = 5 V).

0.0 1.0 2.0 3.0VGS (V)

Linear Dependence on VGS

Sub-Threshold Conduction

0.0 1.0 2.0 3.0VGS (V)

Subthreshold exponential region

Linear region

Latchup

(a) Origin of latchup (b) Equivalent circuit

Rpsubs

Rnwell p-source

n-source

n+ n+p+ p+ p+ n+

p-substrateRpsubs

Rnwell

n-well

SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular

MAIN MOS SPICE PARAMETERS

SPICE Transistors Parameters

SPICE Parameters for Parasitics

Technology Evolution

The CMOS Inverter: A First Glance

Vin Vout

VTC of Real Inverter

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

Dynamic Behavior of MOS Transistor

CGDCGS

CSB CDBCGB

Delay Definitions

VDD VDD

VinVout

M4Cdb2

Fanout

Interconnect

VoutVin

SimplifiedModel

CMOS Inverters

Polysilicon

Metal1

1.2 m=2

Using Cascaded Buffers

1 u u2 uN-1

In Out

uopt = e

COMBINATIONAL LOGIC

Static CMOS

PUN and PDN are Dual Networks

PMOS Only

NMOS Only

Example Gate: NAND

4-input NAND Gate

In1 In2 In3 In4

Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

SEQUENTIAL LOGIC

Master-Slave Flip-Flop

MASTER SLAVE

PRESET

The Ellmore Delay

The Clock Skew Problem

CL1 R1 CL2 R2 CL3 R3In Out

t’ t’’ t’’’

tl,min

tl,max

tr,min

tr,max

Clock Edge Timing Depends upon Position

Clock Rates as High as 500 Mhz in CMOS!

Digital Integrated Circuits© Prentice Hall 1995 Devices The MOS Transistor

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