Digital Circuits to Compensate for Energy Harvester Supply Variation

Digital Circuits to Compensate for Energy Harvester Supply Variation

Hao-Yen TangDavid Burnett

Energy-harvesting system

• Battery• Solar cell• TEG(Thermoelectric)• RF coupling• Problem:

voltage ripple

Voltage ripple

EnergyHarvester

On-chip Storage capVLSI block

Energy harvester-powered integrated system

~1nF

Y. Ramadass and A. Chandrakasan, “A battery-less thermoelectric energy harvesting interface circuit with 35 mv startup voltage,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 1, pp. 333–341, Jan.

precharged

Possible solution

• Work with minimum voltage• Supply regulation (with LDO)• Modified basic cells (Razor)• Dynamic clock period adjusting

Proposed solution

Using a Delay-Lock Loop(DLL) to lock the clock period to critical path delay

HW2 decoder circuit(4x cascaded)

Clock Generator (Voltage-Control Oscillator)

Clock Generator (Voltage-Control Oscillator)

• No crystal• Ring oscillator• Supply

Sensitivity

Clock Generator (Voltage-Control Oscillator)

Critical Path duplica

• Extra delay result from simultaneous incoming signal

• Need to be reset every cycle

• 1 clock cycle measure1 clock cycle reset

Clock Generator (Voltage-Control Oscillator)

PFD and loop filter

• Traditional PFD• Charge pump with

constant gm bias• Second order loop

filter for stability

Simulation result

Supply Voltage

VCO control signal

Extra power overhead: 40.2uW (12.7% of the reference VLSI block)

Comparison table

Technique This work Supply

regulation[2]

Modified Basic

Cell[3]Dynamic VDD

adjusting[7]Topology Dynamically

adjust clock period

Fix the supply voltage with LDO

Modify basic cells to detect errors

Dynamically adjust clock period by adjusting analog supply voltage

Hardware overhead

1 extra DLL1 critical path

duplica

1 LDO Peripheral circuits in each cell

(proportional to VLSI block size)

1 LDO

Main issue Response time Large percentage of power wasted in

LDO

Need to modify original VLSI block, hardware overhead

proportional to VLSI block size

Extra power line, power loss in LDO,

need crystal to provide a reference

clock

Acknowledgement

• Prof. Bora <3• EE241 classmates• Dear teammate