Did Power Management Break My CDC Logic? An Integrated ......An Integrated Approach to Power Domain...

Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and

Clock Domain Crossing Verification

1

Ashish Amonkar, Principal Design Engineer, Cypress Semiconductor,

Kurt Takara, Mentor, a Siemens Business,

Avinash Agrawal, Mentor, a Siemens Business,

AGENDA

2

• CDC P checks – Why,Challenges

• CDC PA checks – Flow

• CDC PA checks – Commands

• CDC PA checks – Testbench integration

Low Power Design & Verification - Why• Problem of Today’s Complex SoC Design:

– Leakage power becoming issue below 65 nm

– Dynamic power remains as an issue for decades

– Market Demands: longer battery, IoT, handheld

• Solution: – Control the Supply

– Partitioning design in multiple power domains• Helps to run the design with different voltage

• Helps to accommodate different ON/OFF etc.

• Conventional HDL do not have notion of power domains – No method to distribute power supply network

– No method for switching power ON or OFF or switching voltage values

• Power management needs to be verified early in the design process

• IEEE-1801/UPF enables power management and verification

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Multi-voltage

Power Gating Power Gating with Retention

Low-power stand by

DVS/AVS

Blocks of chip can run 1.2V, 1.0, 0.9V

Some block of chip is OFF, while other running in 1.2V, 1.0V, 0,9V

The OFF block state and data can be retain

Some blockmay need to run at possible low voltage to hold state and data

Dynamic voltage scaling and adaptive voltage scaling is very performance dependent

Chip Power Management Trends

AAA, Integrated Approach to Power Domain/Clock domain crossing checks May 2019

Power Aware Design – UPF • In Design Verification and Implementation Flow (DVIF)

– UPF is a TCL based language provides the notion of Power Intent

• Power Intent - actually the power specification of a designe.g.

– How many power domains are required in the design?

– How to define the primary supply for each domain?

– What protection strategies are required?

• UPF LRM IEEE-1801: specifies syntax/semantics to define power intents – There are multiple version of UPF from 1.0, 2.0, 2.1, 3.0 …

• However, UPF works as a side file with HDL in the DVIF

• The verification and implementation tools– Share common semantics and extends the HDL with UPF artifacts

Your Initials, Presentation Title, Month Year4

create_power_domain –elements {.}

set_isolation <-clamp_value –

isolation_signal …>

……

Power Aware Verification - Why

• Partitioning Issues:– Incorrect implementation of system power modes– Cyclic domain state interdependencies

• Control Sequence Issues:– Power down/up control sequence errors– Power state transition and sequencing errors– Failure to reset after power down/up

• Power Management Issues– Incorrectly structured power switching network– Incorrect powering of logic elements

• Structural Issues:– Missing, incorrect, or redundant isolation strategies and/or cells – Missing, incorrect, or redundant strategies and/or level shifters– Missing, incorrect, or redundant strategies and/or retention registers

Your Initials, Presentation Title, Month Year

PA Dynamic

Verification

PA Static

Verification

5

CDC Power Aware Verification - Why

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• CDC-PA handles UPF-extended HDL designs by doing two things:

– Static verification of the UPF logic.

– Analysis of clock domain crossings involving UPF logic.

• CDC analysis of the design with UPF logic can uncover clock domain crossing issues where both power domains and clock domains are involved

Table 1. CDC-PA Schemes

Scheme Description

pa_combo_logic

UPF adds combinational logic to a crossing.

pa_iso_en_no_sync

UPF isolation cell enable signal does not have a proper synchronizer.

CDC Power Aware Design - Challenges

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• Are isolation signals in the correct clock domain?

• Are isolation cells introducing combinational logic violations to CDC synchronizers?

• Are retention signals in the correct clock domain?

CDC PA checks - Why• Scenario 1: Synchronizer set at the iso enable generation (stbus)

• Scenario 2: Synchronizer set at the iso output

CD

D Q

cdc_path

CD

D Q

CD

D Q

EN

Iso enable generation

CD

D Q

CD

D Q

CD

D Q

CD

D Q CD

D Q

CD

D Q

cdc_path 1

cdc_path 2

Iso enable generation

8 Your Initials, Presentation Title, Month Year

CDC PA Checks - PowerAware Retention Crossing

• Retention cell adds paths to save and restore pins

• New CDC violation B1=>B2

Retention Cell

c2

save

resto

reB2

PD1

c1

B1

c2

Power Control

9 Your Initials, Presentation Title, Month Year

CDC PA Checks - Isolation Enable Missing Synchronizer

• Blocks B1&B2 are in clock domain c1

• Iso_en comes from block B3 in clock domain c2

• New violation for the new CDC path B3->B2

ISO

c1

c2

c1

B3

B2B1

iso_en

Isolation enable signal does not have proper synchronizer.

(pa_iso_en_no_sync)

10 Your Initials, Presentation Title, Month Year

CDC PA Checks - Isolation Causes Combo-logic Violation

• Synchronized CDC path B1->B2 (clock domain c1 to c2)

• Isolation cell introduces combinational path before synchronizer

Power aware combinational logic before synchronizer. (pa_combo_logic)

ISO

c1

B3

c2

B2B1is

o_en

c2

B2

Sync

11 Your Initials, Presentation Title, Month Year

CDC PA checks - Flow

HDL Logic

Design

HDL

Compilation

Power

AnnotationUPFCDC Analysis

Review &

Debug

12 Your Initials, Presentation Title, Month Year

CYPRESS PA CDC FLOW

13 Your Initials, Presentation Title, Month Year

GENERATE PARAMETRIC UPF USING TCL SCRIPT

COMPILE RTL WITH SAME SET OF PARAMETERS

RUN CDC WITH RTL + UPF

CDC PA checks – Questa Support

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qverify -c -do " \

onerror {exit 1}; \

cdc run -d top -pa_upf my.upf; \

exit 0"

qverify -c -do " \

onerror {exit 1}; \

cdc run -d top -pa_upf my.upf; \

cdc generate crossings crossings.rpt; \

cdc generate pa pa_design_detail.rpt -design; \

exit 0"

PA CDC Results

15 Your Initials, Presentation Title, Month Year

Power Domains

PrimaryClocks

Isolation Cells Retention Registers

Subsytem 5 10 286 0

Power

Domain

Registers Latches Isolations Level-Shifters Retentions

PD1 8187 569 1 0 0

PD2 5613 122 83 0 0

PD3 1029 25 201 204 0

PD4 0 0 1 1 0

PD5 0 1 0 0 0

POWER DOMAIN RESULTS

PA CDC Violations

16 Your Initials, Presentation Title, Month Year

Isolation enable signal does not have proper synchronizer. (43378)

Power-aware combinational logic before synchronizer. (14)

Power-aware fanin logic from multiple clock domain (10)

Conclusion

Your Initials, Presentation Title, Month Year17

• RTL CDC verification is a must-have

• Low power elements added to the design after RTL CDC verification

• Power Aware CDC analysis run on RTL and UPF

– Enables verification before netlist is available

– Prevents detection of expensive late stage CDC bugs at the gate-level

Acknowledgements

Your Initials, Presentation Title, Month Year18

• Progyna Khondkar, Mentor Graphics

• Avinash Agrawal, Mentor Graphics

• Kurt Takara, Mentor Graphics