Device Design Considerations for Ultra-Thin Body Non ... · Device Design Considerations for...

Device Design Considerations for

Ultra-Thin Body Non-Hysteretic

Negative Capacitance FETs

Chun Wing Yeung, Asif Khan

Sayeef Salahuddin, Chenming Hu

EECS, UC Berkeley

3RD BERKELEY SYMPOSIUM ON

ENERGY EFFICIENT ELECTRONIC SYSTEMS

1

• Introduction

• Background of Negative Capacitance

FET (NCFET)

• Design considerations

• Simulation of UTB NCFET

• Conclusion

Outline

2

Node

(nm)

250 180 130 90 65 32 14

Vdd

(V)

2.5 1.8 1.3 1.2 1.1 0.9 0.8

Vdd scaling is slowing down

3

IC Vdd scaling history and ITRS projection

Boltzmann statistics lead to 60mV/decade limit.

Source: C. Hu, IEDM 2010

Tunnel FET

Band-To-Band

Tunneling

• Reverse-biased

P-I-N

Feedback

FET A Padilla, IEDM 2008

Internal Feedback

• Forward-biased

P-I-N

Negative

Capacitance FET S. Salahuddin,

Nano lett. 2008

Negative

Capacitance

Amplification

Sub-60mV/dec Swing FETs

4

SWITCHING MECHANISM STRUCTURE

N+i-Si

Gate

P+

BOX

VG

Gate

Lg

VD>0V

Gate

N++

P++

i-Si

Gate

VD > 0

The Negative Capacitor

5

Khan et al. APL 99, (2011) Landau Theory of

Ferroelectric

The Negative Capacitance

Region

6

V (v)

Q (C/cm^2)

𝑵𝒆𝒈𝒂𝒕𝒊𝒗𝒆 𝑪𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆

𝑹𝒆𝒈𝒊𝒐𝒏

𝑷𝒐𝒔𝒊𝒕𝒊𝒗𝒆 𝑪𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆

𝑹𝒆𝒈𝒊𝒐𝒏

|CFE|

Capacitance Model for

Negative Capacitance FET

Schematic of NCFET

CMOS

VG

Underlying

MOSFET

CFE

Cox

Cdep

ᵠs

VMOS

Capacitance Model of NCFET

Capacitive Divider

8

VG

CFE

CMOS

VMOS

𝑽𝑴𝑶𝑺 = 𝑽𝑮

𝑪𝑭𝑬

𝑪𝑭𝑬 + 𝐶𝑴𝑶𝑺

𝑽𝑴𝑶𝑺 = 𝑽𝑮

|𝑪𝑭𝑬|

𝑪𝑭𝑬 − 𝐶𝑴𝑶𝑺

Since CFE can be negative:

A𝑽 =𝜕𝑉𝑀𝑂𝑆

𝜕𝑉𝐺=

𝐶𝐹𝐸

𝐶𝐹𝐸 − 𝐶𝑀𝑂𝑆

𝑽𝑴𝑶𝑺 = 𝑽𝑮 ∗? ?

Condition 1:

For large amplification,

|CFE| should be close to CMOS

Use Negative Capacitance to Reduce the

Subthreshold Swing

Schematic of Negative Capacitance FET VG

Underlying MOSFET

CMOS

CFE

Cox

Cdep

ᵠs

𝑺𝑺 𝒐𝒇 𝑵𝑪𝑭𝑬𝑻 = 𝟔𝟎𝒎𝑽/𝒅𝒆𝒄 ∗ 𝟏 + 𝑪𝒅𝒆𝒑

𝑪𝒐𝒙∗

𝟏

𝑨𝑽

Subthreshold Swing of NCFET

𝑺𝑺 𝒐𝒇 𝑵𝑪𝑭𝑬𝑻 = 𝟔𝟎𝒎𝑽/𝒅𝒆𝒄 ∗ 𝟏 + 𝑪𝒅𝒆𝒑

𝑪𝒐𝒙−

𝑪𝒅𝒆𝒑

|𝑪𝑭𝑬|

Condition 2:

For swing < 60mV/dec

|CFE| < Cox

(sets the maximun value for |CFE|)

VG

Cox’

CFE

Cox

Cdep

ᵠ Cox’ = 𝑪𝒐𝒙∗|𝑪𝑭𝑬|

𝑪𝑭𝑬

−𝑪𝒐𝒙

Condition for no hysteresis

𝑺𝑺 𝒐𝒇 𝑵𝑪𝑭𝑬𝑻 = 𝟔𝟎𝒎𝑽/𝒅𝒆𝒄 ∗ 𝟏 + 𝑪𝒅𝒆𝒑

𝑪𝒐𝒙−

𝑪𝒅𝒆𝒑

|𝑪𝑭𝑬|

For stable operation (no hysteresis): 𝑪𝒅𝒆𝒑

𝑪𝒐𝒙−

𝑪𝒅𝒆𝒑

|𝑪𝑭𝑬| must be larger than -1

𝑪𝒅𝒆𝒑

𝑪𝒐𝒙−

𝑪𝒅𝒆𝒑

|𝑪𝑭𝑬| > -1

𝟏

|𝑪𝑭𝑬| <

𝟏

𝑪𝒐𝒙 +

𝟏

𝑪𝒅𝒆𝒑

|CFE| > CMOS

Condition 3:

For no hysteresis, |CFE| must be

larger than CMOS

(sets the minimum value for |CFE|)

A𝑽 =𝐶𝐹𝐸

𝐶𝐹𝐸 − 𝐶𝑀𝑂𝑆

The “window” of CFE

12

-2 -1 0 1 2

0

4

8

Ca

pa

cita

nce

(a

u)

VG (V)

CMOS

COX Condition 2:

If swing < 60mV/dec

=> |CFE| < Cox

Condition 3:

For no hysteresis, |CFE|

must be larger than CMOS

Condition 1:

For small swing, CFE should

be ~ CMOS

Choosing the |CFE| value

13

-2 -1 0 1 2

0

4

8

Capacitance (

au)

VG (V)

𝐶𝐹𝐸

CMOS

The Capacitance Mismatch

14

-2 -1 0 1 2

0

4

8

Capacitance (

au)

VG (V)

Av=𝐶𝐹𝐸

𝐶𝐹𝐸 −𝐶𝑀𝑂𝑆

𝐶𝐹𝐸

VG

CMOS

CFE

CMOS

0.0 0.2 0.4 0.6 0.8 1.00

5

10

15

20

V

CMOS

/CFE

What do we need?

15

-2 -1 0 1 2

0

4

8C

MO

S (

au

)

VG (V)

We need a underlying MOSFET with

a larger depletion capacitance.

Device Optimization:

UTB with Extremely Thin BOX

16

VG

CMOS

CFE

Cox

Cs

ᵠ

CBOX

“Cdep”

p+ Si

i- Semiconductor N+N+High-K Oxide

Metal

Ferro-electric

VD

VG

Buried Oxide

By using a thin body and a thin

BOX, Cdep can be increased

p+ Si

i- Semiconductor N+N+High-K Oxide

Metal

Ferro-electric

VD

VG

Buried Oxide

Simulation of Negative

Capacitance FET Structure Coupled 2D Electrostatics-1D Landau Simulation Ferroelectric: 1-D Landau Simulation. PbZr0.5Ti0.5O3. Anisotropy Constants from Haun et al., Ferroelectrics 99, 63 (1989) Intrinsic MOSFET (2D): TCAD Sentaurus Simulation. Interlayer Metallic Electrode: To screen out non-uniformity in potential profile as well due to domain formation.

Effect of varying TS

18

0.0 0.1 0.2 0.3 0.4 0.510

-6

10-3

100

103

I DS (

µA

/µm

)

VGS

(V)

Ts=0.5nm

Ts=1nm

Ts=2nm

VG

CMOS

CFE

Cox

Cs

ᵠ

CBOX

“Cdep”

Simulated Id-Vg of

UTB NCFET

19

0.0 0.2 0.4 0.6 0.8 1.010

-6

10-3

100

103

~18mV/dec

~22mV/dec~235mV/dec

WIthout FE

Vds=0.05

Vds=0.5

WIth FE

Vds=0.05

Vds=0.5

I DS (

µA

/µm

)

VGS

(V)

Lg=32nm, Ts=0.7nm, Tox=3nm, Tbox=1nm

Summary

20

200 300 400 50015

20

25A

vg

.SS

(m

V/d

ec

)

VDD

(mV)

LG=32nm

tS=0.7nm

tBOX

=1nm

tOX

=3nm

100

200

300

400

IO

N (µA

/µm

)

• NCFET can operate hysteresis free.

• For sub-60mV/dec and no hysteresis,

there is a maximum and minimum

constraint for CFE.

• UTB design can reduce the issue of

capacitance mismatch.

• Simulation shows NCFET can achieve

swing of sub-30mV/dec from pA/μm to

μA/μm with estimated ION of 0.250mA/μm

at 0.3V VDD

Conclusion

21

Acknowledgements

This work was partially supported by Office of Naval

Research, the FCRP MSD center, Qualcomm, and

NSF E3S Center at Berkeley.

22

• Thank you!

23

•𝜕𝜑𝑠

𝜕𝑉𝐺=

𝜕𝜑𝑠

𝜕𝑉𝑀𝑂𝑆∗

𝜕𝑉𝑀𝑂𝑆

𝜕𝑉𝐺=

𝐶𝑜𝑥

𝐶𝑜𝑥+𝐶𝑑𝑒𝑝∗

𝐶𝐹𝐸

𝐶𝐹𝐸 −𝐶𝑀𝑂𝑆

•𝜕𝜑𝑠

𝜕𝑉𝐺=

𝐶𝑜𝑥

𝐶𝑜𝑥+𝐶𝑑𝑒𝑝∗

𝐶𝐹𝐸

𝐶𝐹𝐸 −𝐶𝑜𝑥𝐶𝑑𝑒𝑝

𝐶𝑜𝑥+𝐶𝑑𝑒𝑝

• SS=𝜕𝑉𝐺

𝜕𝑉𝑀𝑂𝑆∗

𝜕𝑉𝑀𝑂𝑆

𝜕𝜑𝑠∗

60𝑚𝑉

𝑑𝑒𝑐

• =60𝑚𝑉

𝑑𝑒𝑐∗ (1 +

𝐶𝑑𝑒𝑝

𝐶𝑜𝑥−

𝐶𝑑𝑒𝑝

|𝐶𝐹𝐸|)

Backup Slide

24

• Ec ~ 30k to 300kV/cm

• ~ 0.003 to 0.03V/nm

25

Material Exploration for Ferroelectric

Negative Capacitance

substrate

SrRuO3

Au

. . .

BSTO

LAO

BSTO

LAO

BSTO

LAO

Ba0.8Sr0.2TiO3-LaAlO3 superlattice

(layer thickness <10nm)

Unpublished

26

Three Different Ferroelectric

Negative Capacitance Model

Systems has been identified so far.

1. Pb(Zr0.2Ti0.8)O3, > 225 0C

2. PbTiO3, > 110 0C

3. (Ba0.8Sr0.2)TiO3 > 110 0C

Negative Capacitance in sub-10nm Films:

Ba0.8Sr0.2TiO3-LaAlO3 superlattice

With three different negative capacitance material system identified,

the stage is set for making the first crystalline NCFET.

MOSFET Scaling: The Negative

Capacitance Approach

Negative capacitance can give S < 60 mV/decade

Moore’s Law Negative Capacitance FET

Salahuddin et al., Nanoletters 8, 405 (2008).

27

Fabrication of Negative Capacitance FET for simultaneous High Performance-Ultra Low Power Operation for Mobile Computing

Ferroelectric Negative

Capacitance

Positive Capacitance Ferroelectric

Negative Capacitance

V C

Capacitor

Landau-Devonshire Theory of Ferroelectrics tells that Ferroelectric capacitors can give rise to negative capacitance

under certain conditions.

28

Epitaxial Growth of

Nanoscale Ferroelectric

Heterostructure

29 Excellent Epitaxial Quality, Interface Roughness 2-3

unit cells

Pulsed Laser Deposition

Material Type a-axis

param

eter

Pb(Zr0.2Ti0.8)

O3

Ferroelec 3.953

A

SrTiO3 Dielectric 3.905

A

SrRuO3 Metal 3.92 A STO substrate

SRO

Dielectric STO

Ferro PZT

Au

Interface

roughness less

than 2-3 unit cell.

TEM Courtesy:

Prof. X. Pan,

UMich

Material Exploration for

Ferroelectric Negative

Capacitance

substrate

SrRuO3

Au

. . .

BSTO

LAO

BSTO

LAO

BSTO

LAO

Ba0.8Sr0.2TiO3-LaAlO3 superlattice

(layer thickness <10nm)

Unpublished

30

Three Different Ferroelectric

Negative Capacitance Model

Systems has been identified so far.

1. Pb(Zr0.2Ti0.8)O3, > 225 0C

2. PbTiO3, > 110 0C

3. (Ba0.8Sr0.2)TiO3 > 110 0C

Negative Capacitance in sub-10nm

Films: Ba0.8Sr0.2TiO3-LaAlO3 superlattice

With three different negative capacitance material system identified,

the stage is set for making the first crystalline NCFET.

31