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8/13/2019 Design Technic
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Super Buffer Design
Driving Large Capacitive Loads
prepared
by
Mr. KOTHANDAPANI R
ME-VLSI DESIGN
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Given a large capacitance load C load How many stages are needed to minimize the delay?
How to size the inverters?
2
Supper Buffer
C load
1 2 N1
C g C dC g
2
C gC d 2 C d N C g N
C dC load
Equiv INV
N: number of inverter stages
: optimal stage scale factor
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where C g: the input capacitance of the first stage inverter. C d : the drain capacitance of the first stage inverter. Each inverter is scaled up by a factor of per stage. C load = N+1C g All inverters have identical delay of
0(C d + C g )/(C d +C g ) which 0 is per gate delay forEquiv INV in ring oscillator circuit with load
capacitance = C g+C d
3
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Consider N stages, each inverter has same delay
0(C d + C g )/(C d +C g ).
Therefore,
C C
C C N
g d
g d total
01
4
1 2 N1
C g C d C g 2 C gC d 2 C d N C g N C d C load
Equiv INV
dd dd
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Goal: Choose and N to minimize total . By C load = N+1C g , we have
Plug the above equation into total , we get
To minimize total :
C C
C C C C
d g
g d g
load
total
0
ln
ln
ln
ln
1
C
C
N g
load
5
0
ln1
ln
1
ln20
C C C
C C C C
C C
d g
g
d g
g d
g
load total
C
C
g
d opt opt 1ln
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For the special case C d =0 ln( opt)=0 opt = e. However, inreality the drain parasitics cannot be ignored.
Example: For C d =0.5 fF, C g=1 fF, determine opt and N for C load =50 pF.
opt (ln opt -1) = 0.5 opt = 3.18
The Super Buffer Design which minimizes total for C load = 50 pF is N=7 Equiv INV stages, and opt = 3.18
36.6
118.3ln/101/1050ln
1ln//ln
ln
/ln1
1412
opt g load
opt
g load
C C N
C C N
6
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Oscillation period T is equal to
T = PHL1+ PLH1+ PHL2+ PLH2+ PHL3+ PLL3 =2 p+2 p+2 p =3·2 p=6 p
For arbitrary odd number (n) of cascade-connected
invertes, we have f=1/T=1/(2·n· p ) Also, we can write
p=1/(2·n·f)
7
V 1
C load,1 C load,2 C load,3
V 2 V 31 2 3
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τ PHL2
V out
V OH
V 50%
t
V OL
τ PLH3 τ PHL1 τ PLH2 τ PHL3 τ PLH1
V 2 V 1 V 3 V 2 V 1 V 3
T
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Figure 8.8 CMOS inverter circuit
High speed design can be obtain fromstudying the characteristic delay throughinverter
n p L
W r
L
W
1''
p
n
p
n
k k r
)(
1
T DD
pnV V
R R R
]1[)( / t
DDout eV t V
/)( t
DDout eV t V
)( L FET out C C R RC
L s C t t 0
)(
1
T DD V V R
)( GpGnox
GpGnin
A AC C C C
Gn
nox
pnoxin
C r
LW C r
W W LC C
)1(
))(1(
)(
)2/( DD M V V
(8.42)
(8.43)
(8.44)
(8.50)(8.45)
(8.48)
(8.49)
(8.46)
(8.47)
(8.51)
(p-network pre-charge function)
(n-network dis-charge function)
(assume ts = tr = t f )
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Figure 8.9, since the load capacitance is the same
as the gate’s own input capacitance , we call this a
unit load value
in L C C 1
in s C t t 01
S '
S
R R '
S
'
L s C S
t t
0
nn SW W '
inin SC C '
(unit load) (8.52)
(switching time)
(When C L >> C in , using S > 1)
(new switching time)
(8.53)
(8.54)
(8.55)
(8.52)
(8.53)
(8.54)
(8.55)
(When C L=S C in , using S > 1)
Figure 8.9 Concept of a unit load
Figure 8.10 Driving a largeinput capacitance gate
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In figure 8.11. To drive the large load capacitance,let the 1-th be the unit gate
Figure 8.11 Inverter chainanalysis
N N 1321 ...
12 S
23 S
j j S 1
12 S
1
2
23 S S
1
3
34 S
1
)1( j
j S
1
)1( C S C j
j
)1(
j j
S
R R
1 j j j C R
Figure 8.12 Characteristics of atypical stage in the chain
(8.60)
(8.61)
(8.62)
(8.63)
(8.64)
(8.65)
(8.66)
(8.67)
cetanctranscondudevice
cetanresis FET R
etanccapaciinput C
1
1
1
(1-th stage parameters)
(assume C j+1 >> C FET,j)
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L N N N
N N d
C R R RC RC RC R
1433221
1321
.. .
...
1
1
C S
C C
N
N L
11
11
1
2
11
3
2
11
2111 .. . C S
S
RC S
S
RC S
S
RC S
S
RSC R N
N
N
N d
)(
.. .
11
1111111111
C SR N
C SRC SRC SRC SRC SRd
r d NS
1C S C N
L
)ln(ln)ln(1
S N C
C S L N
)ln(
ln1
S
C
C
N
L
)ln(ln1 S
S
C
C Lr d
0)ln(
S
S
S S
d
1)ln( S or
eS
1
1ln
)ln(
ln
C
C
S
C
C
N L
L
r
L
d C
C
e
1ln
Figure 8.13 Time constants in the cascade
(8.68)
(8.69)
(8.70)
(8.71)
(8.72)
(8.73)
(8.74)
(8.75)
(8.77)
(8.78)
(8.79)
(8.80)
(8.81)
(8.76)
(8.82)
(N stages)
11, C Rwhere r
0)][ln()ln(
12
S S
S
S
(e = 2.71…)
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Figure 8.14 shows the j-th stage circuit with the parasitic FET
capacitance C Fj included at the output S > e (in physical design)
Figure 8.14 Driver chain withinternal FET capacitance
)( 1, j j F j j C C R
1,
)1(
, F
j
j F C S C
)(...)()( ,32,221,1 L N F N F F d C C RC C RC C R
)( 111,1 C SR N C NR F d
1
ln)ln()ln( C
C
S
S
S
Lr
xd
1,1 F x C Rwhere
r
xS S
1)ln(
(8.68)
(8.69)
(8.70)
(8.71)
(8.72)
(8.73)
(8.74)
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