Design and Implementation of VLSI Systems (EN1600) Lecture 31: Array Subsystems (PLAs/FPGAs)

S. Reda EN1600 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 31: Array Subsystems (PLAs/FPGAs)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson - Maxfield]

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Using ROMs to implement logic

ROM(truth table)

Inputs Outputs

In most designs, using ROMs can be extremely inefficient in terms of area

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Programmable logic arrays

• A Programmable Logic Array performs any function in sum-of-products form.

• Literals: inputs & complements• Products / Minterms: AND of literals• Outputs: OR of Minterms• Example: Full Adder

out

s abc abc abc abc

c ab bc ac

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b coutc

Minterm

s

Inputs Outputs

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NOR-NOR PLAs

• ANDs and ORs are not very efficient in CMOS• Dynamic or Pseudo-nMOS NORs are very efficient• Use DeMorgan’s Law to convert to all NORs

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

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PLA schematic and layout

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

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PLAs vs. ROMS

• PLAs are more flexible than ROMs– No need to have 2n rows for n inputs– Only generate the minterms that are needed– Take advantage of logic simplification

• PLAs are popular for small-scale circuits that have 2-level implementations

• PLAs are not scalable to implement large designs

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Programmable logic blocks (lookup tables)

|

&ab

cy

y = (a & b) | !c

Required function Truth table

1011101

0000010100111001011101111

y

a b c y

00001111

00110011

01010101

10111011

SRAM cells

Programmed LUT

8:1

Mul

tiple

xer

a b c

Programming information could be stored in SRAM or FLASH4-input LUT is the typical size

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FPGA architecture

Programmableinterconnect

Programmablelogic blocks

4-inputLUT

flip-flop

clock

muxy

qe

abcd

Switchbox

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To implement in FPGAs, designs need to be decomposed and mapped to LBs

Map to a LUT in a LB

[Figure form Cong FPGA’01]

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Programmable interconnects (local)

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Programmable interconnects (global)

Switchbox

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Example

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Programming the FPGA

Configuration data in

Configuration data out

= I/O pin/pad

= SRAM cell

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FPGAs versus custom chips

• Offer flexibility → FPGAs can be reprogrammed to perform different logic functions

• No layouts, no masks, no custom fabrication → huge savings for low, med-volume production

• Larger overhead in area, performance, and power