CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)

1 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)

CPRE 583Reconfigurable ComputingLecture 1: Wed 8/26/2009

(Course Overview, VHDL Overview 1)

Instructor: Dr. Phillip Jones(phjones@iastate.edu)

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USA

http://class.ece.iastate.edu/cpre583/

Class Introduction• Class Survey (by next class, phjones@iastate.edu)

– Background (year in school, VHDL/Verilog, EE/CPRE background, ISU login ID)

– What would you like to get from this class

• Syllabus

• Course Expectations– Reinforce research fundamentals– Asking the right question

• VHDL handbook (source Synplicity)– http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)

• VHDL online tutorials– http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html– http://www.vhdl-online.de/tutorial/

• Basic objectives and topics covered in this class.

• VDHL is NOT a programming language. It is a means to describe hardware.

What you should learn

Main topicsAgenda

1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL

2. Computation Models (2.5 Weeks)

3. Applications / Concerns of FPGAs (4 Weeks)

4. Mapping logic to FPGAs (3 Weeks)

5. Case Studies (1 Week)

• Basic components of an FPGA (Chapter 1)

• Overview of ways in which reconfigurable computing can be integrated into a system (Chapter 2)

• Examples of reconfigurable systems (Chapter3)

• Managing the reconfiguration of systems (Chapter 4)

Main topics

opcode {+, -, AND, OR}

Behavior VHDL: ALUcompnt ALU (A,B,opcode,X) case opcode when => opPlus X <= A + B; when => opSub X <= A – B; when => opAND X <= A and B; when => opOR X <= A or B; end case;end component;

Structural VHDL: ALUcomponent ALU (A,B,opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X);end component;

Agenda

Main topicsAgenda

4:1Mux

ALUStructural VHDL: ALUcomponent ALU (A,B,opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X);end component;

Main topicsAgenda

Abstraction that allows– Reasoning about computation

• Correctness• Extraction of parallelism

– Transformations for optimization– Guarantee Properties

Main topicsAgenda

Function1

Function2

Function4

Function3

Main topicsAgenda

Function5

Function1

Memory

Function2

Function3

Function4

Memory

Main topicsAgenda

• Streaming Applications

• Data Parallel Applications

• Fix/Floating Point Computations

• Performance Trade-offs

• Fault Tolerance

Main topics

addABX A

BxorAB

andABX A

0 00 11 0 1 1

A B X0110

0 00 11 0 1 1

A B X0110

0 00 11 0 1 1

A B X0001

0 00 11 0 1 1

A B X0111

2-input Look Up Tables (LUTs)FPGA

LUT LUT LUT LUT

Agenda

X <= A+B; X <= A xor B; X <= A and B; X <= A or B;

Main topics

LUT addAB LUT LUT

LUT xorABLUT LUT

LUTandAB LUT LUT

LUT orAB LUT LUT

Agenda

addABX A

BxorAB

andABX A

0 00 11 0 1 1

A B X0110

0 00 11 0 1 1

A B X0110

0 00 11 0 1 1

A B X0001

0 00 11 0 1 1

A B X0111

2-input Look Up Tables (LUTs)

X <= A+B; X <= A xor B; X <= A and B; X <= A or B;

Main topics

Lectures on interesting uses of FPGAs. Ideally covering topics that the class would like to learn more about.

Please give suggestions as the semester progresses.

Agenda

Machine Problems (MPs)Agenda

0. Platform Introduction

1. Network String Matching

2. Image: Edge Detection

3. Image: PPC coprocessor

4. Final Projects(~6 weeks)

Machine Problems (MPs)

ML507Agenda

PC SerialUART Echo.vhd

PC SerialUART

Echo.vhd(Modify to

capitalize only (a-z))

PC Echo.vhdEthernet(UDP/IP)

PCEcho.vhd

(Modify to count strings (e.g. corn!))

Ethernet(UDP/IP)

PC Echo.vhdEthernet(UDP/IP)

PCEcho.vhd

(Edge detection)Ethernet(UDP/IP)

PC Display.cEthernet(UDP/IP)

Power PC

User Defined Instruction

Monitor VGA

Power PC

Monitor VGA

Power PC

Monitor VGA

• Choose your own topic

• Groups of 2-3 (maybe 4 for a large enough project)

• Encouraged to take on aggressive projects

Review Syllabus

• Objects

• Expectations

• Grading breakdown

• MP grading policy: (more flexible for Distance Students)– Up to 5% added for early completion (Fri Midnight)– -5% after Fri Midnight– -10% additional after Monday Midnight– -10% additional after Tue Midnight– After Wed Midnight will make a note.

What is Reconfigurable Computing?

• Ask wiki: http://en.wikipedia.org/wiki/Reconfigurable_computing

• Computing on a medium that is not fixed• Examples:

– rDPA (course grain reconfiguration)– FPGA (fine grain reconfiguration)– General Purpose Processor (not really)

underlining hardware typical executes a relatively small fixed instruction set.

What are rDPAs?

• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects

ALU ALU ALU

Example

What are rDPAs?

ALU ALU ALU

Example

What are rDPAs?

ALU ALU ALU

Example

What are FPGAs?

• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates

CLB CLB CLB CLB

Configurable Logic Block

What are FPGAs?

CLB CLB CLB

CLB CLB CLB CLB

What are FPGAs?

CLB CLB

CLB CLB CLB CLB

Some FPGA Details

CLB CLB

Some FPGA Details

CLB CLB

LUTABCD

4 input Look Up Table

00000001

11101111

ABCD Z

Some FPGA Details

CLB CLB

LUTABCD

00000001

11101111

ABCD Z

Some FPGA Details

CLB CLB

LUTABCD

00000001

11101111

ABCD Z

Some FPGA Details

CLB CLB

LUTABCD

X000X001

X110X111

ABCD Z

2:1Mux

Some FPGA Details

CLB CLB

LUTABCD

Some FPGA Details

CLB CLB

LUTABCD

PIP Programmable Interconnection Point

Some FPGA Details

CLB CLB

LUTABCD

PIP Programmable Interconnection Point

FPGA Usage Models

FastPrototyping

PartialReconfiguration

FullReconfiguration

ParallelApplications

System onChip (SoC)

•Experimental ISA

•Experimental Micro Architectures

• Image Processing

• Computational Biology

CPU + Specialized HW - Sparc-V8 Leon

• Remote Update

• Fault Tolerance

• Run-time adaptation• Run-time Customization

Development Platform Overview

• ML507 Evaluation Platform User Guide (pgs. 14-16)– http://www.xilinx.com/support/documentation/boards_and_kits/

ug347.pdf

Machine Problem 0 (MP0) Short Overview

• Officially assigned Fri (8/28), Due Friday (9/4). – Note: 1 week

• Purpose: Make sure you can run the tools. Very light VHDL coding.

• Primary Tasks:– Run the echo circuit without modifications– Run the echo circuit with a modification to convert lower

case ASCII characters to upper case.

• Distance Students: Test using NX for remotely access xilinx.ece.iastate.edu. You can download the NX client from:– For Windows: http://www.nomachine.com/download-client-windows.php– For Linux: http://www.nomachine.com/download-client-linux.php– For MAC OS: http://www.nomachine.com/download-client-macosx.php– For Solaris: http://www.nomachine.com/download-client-solaris.php

VHDL basics

• VHDL: (V)HSIC (H)ardware (D)escription (L)anguage– VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit

• It is NOT a programming language!!!

• It is a Hardware Description Language (HDL)

• Conceptually VERY different form C,C++

• Some links to VHDL tutorials– http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html– http://www.vhdl-online.de/tutorial/– http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)

Some Key Differences from C

• C is inherently sequential (serial), one statement executed at a time

• VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

C example VHDL example

A = B + CX = Y + ZAns = A + X

Initially: A,B,C,X,Y,Z,Ans =1