Comprehensive Ultrasound Research Platform Emma Muir Sam Muir Jacob Sandlund David Smith Advisor:...

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Comprehensive Ultrasound Comprehensive Ultrasound Research PlatformResearch Platform

Emma MuirSam MuirJacob SandlundDavid Smith

Advisor: Dr. SánchezCo-advisor: Dr. Irwin

22

OutlineOutlineIntroductionSystem

◦ Block Diagram / Functional Description◦ Requirements

Progress

33

OutlineOutlineIntroductionSystem

◦ Block Diagram / Functional Description◦ Requirements

Progress

3

44

Ultrasound IntroductionUltrasound IntroductionPiezoelectric Transducer

◦Pulse ExcitationChanges in density reflect waves

55

ObjectiveObjectiveCreate an Ultrasound Research Platform

◦ Image Creation◦Multi-pin

Beamforming

◦Sigma Delta Architecture 1-bit ADC

◦Arbitrary Waveforms Coded excitation signals Configurable delays

5

66

MotivationMotivationImprove Ultrasound TechniquesMedical Applications

◦Detecting tumors and abnormalitiesFuture Research

6

77

SignificanceSignificanceTest codes (arbitrary) for

better imagingMulti-pin to allow

BeamformingArchitecture reduces cost

and size◦RASMUS

Two 19 inch racks

◦Sigma Delta vs. 12+ bit DAC

7

88

OutlineOutlineIntroductionSystem

◦ Block Diagram / Functional Description◦ Requirements

Progress

8

99

Block DiagramBlock Diagram

1010

PC Data ProcessingPC Data Processing

Pulse Compression

Delay Sum Beamforming

Time-Gain Compensation

Envelope Detection

GUI

Receive Data

Log Compression

1111

OutlineOutlineIntroductionSystem

◦ Block Diagram / Functional Description◦ Requirements

Progress

11

1212

System RequirementsSystem RequirementsUp to 8 transducer channelsExcitations <= 3 μs

◦Time-bandwidth product of 40High frequency design

◦Signal to noise ratio (SNR) > 50 dB

13

Sigma Delta ModulationSigma Delta Modulation

< 10% MSE500 M samples/secondTrade off

◦Accuracy vs. Stability◦OSR = 16 (must be a power of 2)◦Order = 2nd

1414

FPGA RequirementsStore data on DDR2

◦62.5 MHz ◦8 waveforms◦1536 bits per waveform

Output Data◦8 Individualized Pins◦Delays of up to 5 s◦500 MHz

1515

FPGA to PC CommunicationUART

◦115200 baudSend waveform dataAssign waveform to pinsAssign delay to pinsStart transmission

1616

Data Processing◦Less than 2 minutes

Display an image ◦Depths between 0.25 cm and 30 cm.◦Adjust contrast

Graphical User Interface (GUI)

1717

OutlineOutlineIntroductionSystem

◦ Block Diagram / Functional Description◦ Requirements

Progress

17

1818

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

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1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

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ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

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1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

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2020

Amplifier ProgressDifferent designs examined

◦H-Bridge

◦2 MOSFETs Push-pull RF MOSFET

◦1 MOSFET N-channel RF MOSFET Final Design

Amplifier Progress

Discuss problems/solutions

Amplifier Progress

Amplifier Progress

Amplifier Progress

Amplifier Progress

Amplifier Progress

T/R Switch ProgressT/R Switch Progress

27

V 15

V 25

0 0

0

U 1TX8 1 0

B11

B22

B33

GN

D4

I N 15

I N 26

I N 37

I N 48

I N 59

I N 61 0

I N 71 1

I N 81 2

O U T11 3

O U T21 4

O U T31 5

O U T41 6

O U T51 7

O U T61 8

O U T71 9

O U T82 0

VB21

VD22

VN23

VP24

V 9

F R E Q = 2 M e gV A M P L = XV O F F = 0

0 0

V 4-5

0 0

V 55

0

V 60

V B

V 75

0

V 85

O U T1O U T2O U T3O U T4O U T5O U T6O U T7O U T8

O U T1R 2

4 0 0

C 1

1 5 p V B O U T2R 3

4 0 0

C 2

1 5 p V BR 4

4 0 0

O U T3

C 3

1 5 p V B O U T4R 5

4 0 0

C 4

1 5 p V B

O U T5R 6

4 0 0

C 5

1 5 p O U T6R 7

4 0 0

C 6

1 5 p O U T7R 8

4 0 0

C 7

1 5 p O U T8V BR 9

4 0 0

C 8

1 5 p V BV BV B V BV B

T/R Switch ProgressT/R Switch Progress

28

Time

0s 0.2us 0.4us 0.6us 0.8us 1.0us 1.2us 1.4us 1.6us 1.8us 2.0usV(OUT1) MAX(V(OUT1))- MIN(V(OUT1))

-1.0V

-0.5V

-0.0V

0.5V

1.0V

1.5V

2.0V

1.92V

PCB ProgressFootprints

◦TX810 Transmit/Receive

Switch

◦RF MOSFET Set INTO board

3030

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

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4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

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3

13

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8

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30

3131

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

12

3

13

7

8

17

31

3232

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

12

3

13

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32

3333

FPGA ProgressArbitrary transmissionOutput verified

◦500 MHzMulti-pin

◦Currently 4◦Adjustable

Arbitrary length◦Must be 256 bit pieces

Adjustable delays of < 33 ms33

3434

FPGA Flowchart Progress

Receive Waveform

Data(UART)

Store to Memory

Is Signal to Transmit

Request Waveform Data

(X8)

Transmit to Pin(X8)

Is Data Received?

No

Delay (X8)Delay (X8)

Yes

34

3535

FPGA RemainingFix storing waveform data from UART

◦ Inconsistent resultsIncrease delays precision

◦After data retrievedMake output more exactChange to 8 pins

35

3636

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

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3

13

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36

3737

UART ProgressUART

◦115200 baud worksPC to FPGA Communication

◦Start transmission signal◦Set waveforms to pins◦Set delays for pins◦Waveform data

Inconsistent

37

383838

Waveform GUI FeaturesWaveform GUI FeaturesMultiple selectionAutomatic pin settings removalSave/Load settingsCheck files exist when loading settingsLet “None” represent an array of 0’s

3939

4040

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

12

3

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40

4141

FPGA Results

-2 -1 0 1 2 3 4

x 10-6

-5

0

5

10

-2 -1 0 1 2 3 4

x 10-6

-5

0

5

10

Time (s)

Time (s)

Delayed

Cross-talk Cross-talk

41

4242

FPGA Results

-5 0 5

x 104

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Normalized Correlation

Sample number

Max Corr. = 0.97

42

4343

FPGA Results

43

4444

FPGA Results

44

4545

FPGA Results

45

4646

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

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3

13

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8

17

46

4747

Analog Front End Results

Source: Analog Devices UG-016 http://www.analog.com/static/imported-files/user_guides/UG-016.pdf

47

4848

AlternativesAnalog Front End

◦12 bit resolution◦80 MSPS

Lecroy High Speed Oscilloscope◦725Zi ◦8 bit Resolution◦20 GSPS◦4 Channels

48

4949

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

12

3

13

7

8

17

49

5050

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

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50

BeamformingBeamforming

Delay based on distance from point to sensor and distance from sensor to focal point

Note: No delay at the Focal Point

Sensors

Focal Point

Point

51

Without Beamforming With Beamforming

52

AttenuationAverage frequency attenuation in tissue

◦ 0.5 dB/cm/MHz ◦ 5e-5 dB/m/Hz

Doubled for ultrasound imagingFrequency = 8MHzMaximum depth = 30cmMaximum attenuation = 240dBImage dB range = 0dB to -50dB

53

Time Gain CompensationBased on depth of point in imageAtt = 1dB/cm/MHzTGC = Att*Depth*8MHzAdd to compensateNote that this increases white noise for

larger depths

54

5555

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

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55

Sigma Delta RepresentationSigma Delta Representation

56

0 1 2 3 4 5 6 7-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 1 2 3 4 5 6-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Without Pre-Enhanced MagnitudeWithout Pre-Enhanced Magnitude

0 0.2 0.4 0.6 0.8 1 1.2

x 10-5

-1

-0.5

0

0.5

1

0 0.2 0.4 0.6 0.8 1 1.2

x 10-5

-1

-0.5

0

0.5

1

Correlation = 0.9763

57

Pre-Enhanced MagnitudePre-Enhanced Magnitude

0 0.5 1 1.5 2 2.5 3

x 10-6

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5 3

x 10-6

-1

-0.5

0

0.5

1

58

With Pre-Enhanced MagnitudeWith Pre-Enhanced Magnitude

0 0.2 0.4 0.6 0.8 1 1.2

x 10-5

-1

-0.5

0

0.5

1

0 0.2 0.4 0.6 0.8 1 1.2

x 10-5

-1

-0.5

0

0.5

1

Correlation = 0.9916

59

Sigma Delta FeaturesSigma Delta FeaturesEasy to modify

◦Frequency◦Period◦Waveform equation◦Number of samples

Pre-Enhanced MagnitudeChecks/displays correlationWrites output to a file as 0’s and 1’s

60

Sigma Delta AdditionsSigma Delta AdditionsGUI interface for entering

◦Frequency◦Period◦Waveform equation

Select location to save fileInterface with Waveform GUI

61

6262

REC ResultsMATLAB simulation150% of original bandwidthLinear chirp frequencies

◦1.14 times the bandwidth◦Reduce side-lobes during pulse compression

Apply to finished system

6363

h1(n) * c1(n) = h2(n) * c2(n)

6464

6565

Pulse Compression Results MATLAB simulationWiener filterSNR of 60 dBInput is REC pre-enhanced chirpVaried Smoothing Factor (SF)

◦Operating Point

6666

6767

Field II Simulations

REC Excitation and Pulse Compression

SF = 0.1

Impulse Excitation 67

6868

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

12

3

13

7

8

17

68

MATLAB GUI FeaturesMATLAB GUI FeaturesDepth from 2mm to 231mmMax dB range from 10dB to 60dBUpdate chart settings automaticallyUpdate data in 54s

6969

MATLAB GUI

70

MATLAB GUI

71

MATLAB GUI AdditionsMATLAB GUI AdditionsDepth from 2mm to 300mmRestrict max dB to 40dB to 60dBAllow user to type value or scrollMinimize update timeConvert to C

7272

7373

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

12

3

13

7

8

17

73

7474

ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

10

11

12

3

13

7

8

17

74

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ProgressID Task Name % Complete

Feb 2011 Mar 2011 Apr 2011

1/23 1/30 2/6 2/13 2/20 2/27 3/6 3/13 3/20 3/27 4/3 4/10 4/17 4/24 5/1

1

4

5

9

14

15

16

40%Design and Test Analog Components

90%Finalize FPGA Signal Transmission

100%Create / Test UART connection logic

100%Design / Test Delay Sum Beamforming

15%Design Analog Front End Settings

90%Design and Test all MATLAB code

100%Design GUI for Depth/Contrast

0%Test Amplifier with Sigma Delta Signal

0%Rewrite MATLAB code in C

70%Test UART / FPGA Outputs

0%Test Analog Front End Capturing

0%Test Complete Analog System/Probe

0%Combine and Test all C Code

0%Test Complete System

0%2011 Student Scholarship Exposition

0%Write Presentation and Final Report

0%Final Presentation

2

6

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75

Additional InformationAdditional InformationVisit

http://cegt201.bradley.edu/projects/proj2011/ultra/index.html

76

7777

Acknowledgments Acknowledgments The authors would like to thank Analog Devices

and Texas instruments for their donation of parts.

This work is partially supported by a grant from Bradley University (13 26 154 REC)

Dr. IrwinDr. LuMr. MattusMr. SchmittAndy Fouts

7878

ReferencesReferences[1] J. A. Zagzebski, Essentials of Ultrasound Physics, St. Louis, MO: Mosby, 1996.

[2] R. Schreier and G. C. Temes. Understanding Delta-Sigma Data Converters, JohnWiley & Sons, Inc., 2005.

[3] R. Schreier, The Delta-Sigma Toolbox Version 7.3. Analog Devices, Inc, 2009.

[4] T. Misaridis and J. A. Jensen. “Use of Modulated Excitation Signals inMedical Ultrasound,” IEEE Trans. Ultrason., Ferroelectr. Freq. Contr., vol. 52, no. 2,pp. 177-191, Feb. 2005.

[5] M. Oelze. “Bandwidth and Resolution EnhancementThrough Pulse Compression,” IEEE Trans. Ultrason., Ferroelectr. Freq. Contr., vol. 54,no. 4, pp. 768-781, Apr. 2007.

[6] Mitzner, Kraig. Complete PCB Design Using OrCad Capture and PCB Editor,Newnes, 2009.

7979

References Cont.References Cont.[7] Montrose, Mark I. Printed Circuit Board Design Techniques For EMC Compliance:A Handbook for Designers, Wiley-IEEE Press, 2000.

[8] J.A. Jensen. Field: A Program for Simulating Ultrasound Systems, Paper presentedat the 10th Nordic-Baltic Conference on Biomedical Imaging Published in Medical &Biological Engineering & Computing, pp. 351-353, Volume 34, Supplement 1, Part 1,1996.

[9] Kai E. Thomenius. Evolution of Ultrasound Beamformers, IEEE Trans. Ultrason., Ferroelectr. Freq. Contr., pp. 1615-1622, 1996.

[10] J.A. Jensen and N. B. Svendsen. Calculation of pressure fields from arbitrarilyshaped, apodized, and excited ultrasound transducers, IEEE Trans. Ultrason.,Ferroelec., Freq. Contr., 39, pp. 262-267, 1992.

[11] Kjærgaard, Nina. "RASMUS." Center for Fast Ultrasound Imaging. Technical University of Denmark, 28 Sept. 2010. Web. 25 Feb. 2011. <http://www.dtu.dk/centre/cfu/English/research/facilities/RASMUS.aspx>.

8080

Questions?Questions?

Without TGC With TGC

81

Using Delta as the Excitation Signal

Using REC (chirp)

82