COE4OI5 Engineering Design Chapter 1: The 15 minutes design

COE4OI5Engineering Design

Chapter 1: The 15 minutes design

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Simple design example• An OR function with two inputs will be designed using

Quartus II CAD tools.

• The design will be entered using schematic capture and VHDL

• The design will be simulated

• An FPGA on the UP3 board will be programmed to implement the OR.

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Design process for schematic or VHDL entry.

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Simple design example (UP3)

• The inputs to the OR gate will be two pushbuttons and the output will be displayed using an LED (all on the UP board no external wiring is required)

• Function: turn on the LED when one OR the other pushbutton is pushed.

• Pushbuttons PB1 and PB2 are connected to pins 62 and 48 (you can get this info from Table 2.4 of the book or the UP3 manual on the CD)

• The pushbuttons are “active low” (connect zero volt to the pins when they are pushed)

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Simple design example (UP3)

• UP3 has four LEDs

• To turn the LED on the board you should output a low signal.

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Connections between the pushbuttons, the LEDs, and the Altera FLEX device.

AlteraFlex

Device

+5V +5V+5V

PB1

PB2

LED

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Equivalent circuits for ORing active low inputs and outputs.

• Since the pushbuttons generate inverted (active low) signals and LED requires inverted signal to turn on, we built an OR gate with inverted inputs and output.

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Figure 1.6 Creating a new Quartus II Project.

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Figure 1.7 Setting the FPGA Device Type.

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• UP3 is available with two different sizes of Cyclone FPGAs: EP1C6Q240C8 and EP1C12Q240C8

• The one in the lab is EP1C12Q240C8

• For UP2 the FPGA is EPF10K70RC240-X

• For number X look at the FLEX chip on the board

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Figure 1.8 Creating the top-level project schematic design file.

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Figure 1.9 Selecting a new symbol with the Symbol Tool.

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Figure 1.10 Active low OR-gate schematic example with I/O pins connected.

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Table 1.1 Hardwired connections on the FPGA chips for the design.

I/O Device

UP 3 Pin Number Connections

UP 1 & UP 2 Pin Number Connections

PB162 (SW7)

28 (FLEX PB1)

PB248 (SW4)

29 (FLEX PB2)

LED56 (D3)

14 (7Seg LED DEC. PT.)

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Figure 1.11 Assigning Pins with the Assignment Editor.

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Figure 1.12 Active low OR-gate timing simulation with time delays.

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Figure 1.13 ALTERA UP 3 board showing Pushbutton and LED locations used in

design

Parallel PortVGAPort

B B B

Santa Cruz Expansion Long Connector

Santa Cruz Expansion Long Connector

Santa Cruz Expansion Long Connector

JP6

On/OffSwitch

PowerConnector

MountingHole

HeatSink

HeatSink

+5 VoltSupplyLED

+3.3 VoltSupplyLED

HeatSink B B

Flash

BReset

GlobalReset

4 User Definable DIP Switches (JP3)

4 Push Buttons

SRAM4 User

DefinableLEDs

Input ClockSetting Headers

Oscillator Chip

Cyclone FPGAEP1C6Q240C8

I2C PROMChip .....

Headersfor I2C

Bus SignalsUSB PHYChip

PS-2Port

USBPort

Invalid Volt. LED

JTAG & ASDownload

Connectors

“B”- Buffer Chips

Liquid Crystal Display

Real Time Clock

J5

J7

JP19

JP4LED

SerialChip

J3

J2 J4

J1

JP19

JP5

JP7JP3

SW7

SW6

SW5

SW4

D3

D4

D5

D6

LEDPushbuttons

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Figure 1.14 ALTERA UP 2 board with jumper settings and PB1, PB2, and LED

locations

Chip Select Jumpers Decimal Point LED

FLEX Pushbuttons

FLEX_EXPAN_C

FLEX_10K

EPF10K20RC240-4 DAA239837

R

R

Mouse

25.175 MHzCLOCK

FLEX_EXPAN_AFLEX_PB1 FLEX_PB2

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

DC_IN FLEX_DIGIT

U1

JTAG_OUT

POWER TCK

MAX_SW1 MAX_SW2

EMP7128SLC84-7 BFD329837

R

R

VGAAdapter

P1

P2

P3P4

P9 P10P6P5

P7 P8

EPC

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MAX FLEX

Table 1.2 Jumper settings for downloading to the UP2 MAX and FLEX devices.

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Figure 1.16 VHDL Entity declaration text.

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Figure 1.17 VHDL OR-gate model (with syntax error).

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Figure 1.18 VHDL compilation with a syntax error.

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Figure 1.22 Timing analyzer showing input to output timing delays.

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Figure 1.23 Floorplan view showing internal FPGA placement of OR-gate in LE and

I/O pins

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Figure 1.24 ORgate design symbol.

orgate

inst

PB1PB1

PB2PB2

LEDLED