COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and...

COE 202Introduction to Verilog

Computer Engineering Department

College of Computer Sciences and Engineering

King Fahd University of Petroleum and Minerals

Outline D Latch

D Flip Flop

Structural Modeling of a Sequential Circuit

FSM Modeling

Parallel Load Register

Shift Register

Up-Down Counter

D Latchmodule dlatch (output q, input data, enable);

assign q = enable ? data: q;

endmodule

module dlatch2 (output reg q, input data, enable);

always @(enable, data)

if (enable == 1'b1) q <= data;

endmodule

D Flip Flop – Synchronous Set/Reset

module dff (output reg q, output q_bar, input data, set, reset, clk);

assign q_bar = !q;

always @(posedge clk) // Synchronous set/reset

if (reset == 1'b1) q <= 0;

else if (set == 1'b1) q <=1;

else q <= data;

endmodule

D Flip Flop–Asynchronous Set/Reset

module dff2 (output reg q, output q_bar, input data, set, reset, clk);

assign q_bar = !q;

always @(posedge clk, posedge set, posedge reset) // Asynchronous set/reset

if (reset == 1'b1) q <= 0;

else if (set == 1'b1) q <=1;

else q <= data;

endmodule

Structural Modeling of a Sequential Circuit

module SeqStruct(output Y, input X, Reset, CLK);

dff2 F0 (B, Bb, DB, 1'b0, Reset, CLK);

dff2 F1 (A, Ab, DA, 1'b0, Reset, CLK);

and (DB, Ab, X);

and (w1, A, X);

and (w2, B, X);

or (DA, w1, w2);

or (w3, A, B);

not (w4, X);

and (Y, w3, w4);

endmodule

FSM Modeling Moore Sequence Detector: Detection sequence is 110

IF 110 found on xThen Z gets ‘1’Else z gets ‘0’End

x

clkz

Reset/0

got1/0

got11/0

got110/1

0

1

0

1 1 0

1

FSM Modelingmodule moore_110_detector (output reg z, input x, clk, rst );

parameter reset = 2'b00, got1=2'b01, got11=2'b10, got110=2'b11;

reg [1:0] state, next_state;

always @(posedge clk)

if (rst) state <= reset;else state <= next_state;always @(state, x) beginz = 0;case (state) reset: if (x) next_state=got1; else next_state=reset;

got1: if (x) next_state=got11; else next_state=reset;

got11: if (x) next_state=got11; else next_state=got110;

got110: begin z=1; if (x) next_state=got1; else next_state=reset; end

endcase

endendmodule

Parallel Load Registermodule Par_load_reg4 #(parameter word_size=4)

( output reg [word_size-1:0] Data_out,

input [word_size-1:0] Data_in,

input load, clock, reset);

always @(posedge clock, posedge reset)

if (reset==1'b1) Data_out <= 0;

else if (load==1'b1) Data_out <= Data_in;

endmodule

Shift Registermodule Shift_reg4 #(parameter word_size=4)

( output Data_out, input Data_in, clock, reset);

reg [word_size-1:0] Data_reg;

assign Data_out = Data_reg[0];

always @(posedge clock, negedge reset)

if (reset==1'b0) Data_reg <= 0;

else Data_reg <= {Data_in, Data_reg[word_size-1:1]};

endmodule

MultiFunction Registermodule MFRegister #(parameter n=3) (output reg [n-1:0] Q, input [n-1:0] I, input s1, s0, clk, reset, SI);

always @(posedge clk)

begin

if (reset==1'b1) Q <= 0; // synchronous reset

else

case ({s1,s0})

2'b00: Q <=Q; // no change

2'b01: Q <= I; // parallel load

2'b10: Q <= {Q[n-2:0], SI}; // shift left

2'b11: Q <= {SI, Q[n-1:1]}; //shift right

endcase

end

endmodule

Up-Down Countermodule Up_Down_Counter2 (

output reg [2:0] count,

input load, count_up, counter_on, clock, reset,

input [2:0] Data_in);

always @(posedge clock, posedge reset)

if (reset==1'b1) count <= 3'b0; else

if (load == 1'b1) count <= Data_in; else

if (counter_on == 1'b1)

if (count_up == 1'b1) count<=count+1;

else count<=count-1;

endmodule