Chapter Three

Last revision: 04/20/23

Arithmetic

• Where we've been:

– Performance (seconds, cycles, instructions)

– Abstractions: Instruction Set Architecture Assembly Language and Machine Language

• What's up ahead:

– Implementing the Architecture

operation

result

• Bits are just bits (no inherent meaning)— conventions define relationship between bits and numbers

• Binary numbers (base 2)0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...decimal: 0...2n-1

• Of course it gets more complicated:numbers are finite (overflow)fractions and real numbersnegative numberse.g., no MIPS subi instruction; addi can add a negative number)

• How do we represent negative numbers?i.e., which bit patterns will represent which numbers?

Numbers

• Sign Magnitude: One's Complement Two's Complement

000 = +0 000 = +0 000 = +0001 = +1 001 = +1 001 = +1010 = +2 010 = +2 010 = +2011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4101 = -1 101 = -2 101 = -3110 = -2 110 = -1 110 = -2111 = -3 111 = -0 111 = -1

• Issues: balance, number of zeros, ease of operations

• Which one is best? Why?

Possible Representations

• 32 bit signed numbers:

0000 0000 0000 0000 0000 0000 0000 0000two = 0ten

0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten

0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten

...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten

0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten

1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten

1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten

1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten

...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten

1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten

1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

maxint

minint

• Negating a two's complement number: invert all bits and add 1

– remember: “negate (+/-)” and “invert (1/0)” are quite different!

• Converting n bit numbers into numbers with more than n bits:

– MIPS 16 bit immediate gets converted to 32 bits for arithmetic

– copy the most significant bit (the sign bit) into the other bits

0010 -> 0000 0010

1010 -> 1111 1010

– "sign extension" (lbu vs. lb)

Two's Complement Operations

• Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101

• Two's complement operations easy

– subtraction using addition of negative numbers 0111+ 1010

• Overflow (result too large for finite computer word):

– e.g., adding two n-bit numbers does not yield an n-bit number 0111+ 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”

Addition & Subtraction

• No overflow when adding a positive and a negative number

• No overflow when signs are the same for subtraction

• Overflow occurs when the value affects the sign:

– overflow when adding two positives yields a negative

– or, adding two negatives gives a positive

– or, subtract a negative from a positive and get a negative

– or, subtract a positive from a negative and get a positive

• Consider the operations A + B, and A – B

– Can overflow occur if B is 0 ?

– Can overflow occur if A is 0 ?

Detecting Overflow

• An exception (interrupt) occurs– Control jumps to predefined address for exception– Interrupted address is saved for possible resumption

• Details based on software system / language– example: flight control vs. homework assignment

• Don't always want to detect overflow— new MIPS instructions: addu, addiu, subu

note: addiu still sign-extends!note: sltu, sltiu for unsigned comparisons

– Roll over:　 circular buffers– Saturation: pixel lightness control

Effects of Overflow

• Problem: Consider a logic function with three inputs: A, B, and C.

Output D is true if at least one input is trueOutput E is true if exactly two inputs are trueOutput F is true only if all three inputs are true

• Show the truth table for these three functions.

• Show the Boolean equations for these three functions.

• Show an implementation consisting of inverters, AND, and OR gates.

Review: Boolean Algebra & Gates

• Let's build an ALU to support the andi and ori instructions

– we'll just build a 1 bit ALU, and use 32 of them

• Possible Implementation (sum-of-products):

operation

result

op a b res

An ALU (arithmetic logic unit)

Appendix: B.5

• Selects one of the inputs to be the output, based on a control input

• Lets build our ALU using a MUX:

Review: The Multiplexor

note: we call this a 2-input mux even though it has 3 inputs!

• Not easy to decide the “best” way to build something– Don't want too many inputs to a single gate– Dont want to have to go through too many gates– for our purposes, ease of comprehension is important

• Let's look at a 1-bit ALU for addition:

• How could we build a 1-bit ALU for add, and, and or?

• How could we build a 32-bit ALU?

Different Implementations

cout = a b + a cin + b cin

sum = a xor b xor cin

CarryIn

CarryOut

Building a 32 bit ALU

Result

Operation

CarryIn

CarryOut

Result31a31

Result0

CarryIn

Result1a1

Result2a2

Operation

CarryIn

CarryOut

CarryIn

CarryOut

CarryIn

CarryOut

CarryIn

R0 = a ^ b;

R1 = a V b;

R2 = a + b;

Case (Op) {

0: R = R0;

1: R = R1;

2: R = R2 }

Case (Op) {

0: R = a ^ b;

1: R = a V b;

2: R = a + b}

• Two's complement approach: just negate b and add.

• How do we negate?

• A very clever solution:

Result = A + (~B) + 1

What about subtraction (a – b) ?

Result

Operation

CarryIn

CarryOut

Binvert

• Need to support the set-on-less-than instruction (slt)

– remember: slt is an arithmetic instruction

– produces a 1 if rs < rt and 0 otherwise

– use subtraction: (a-b) < 0 implies a < b

• Need to support test for equality (beq $t5, $t6, $t7)

– use subtraction: (a-b) = 0 implies a = b

Tailoring the ALU to the MIPS

Supporting slt

• Can we figure out the idea?0

Result

Operation

CarryIn

CarryOut

Binvert

Result

Operation

CarryIn

Binvert

Overflowdete ction

Overflow

Seta31

ALU0 Result0

CarryIn

Result1a1

Result2a2

Operation

Result31

Overflow

Binvert

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

Test for equality

• Notice control lines:

000 = and001 = or010 = add110 = subtract111 = slt

•Note: zero is a 1 when the result is zero!

Seta31

Result0a0

Result1a1

Result2a2

Operation

Result31

Overflow

Bnegate

ALU0Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn0

Result

Operation

CarryIn

CarryOut

Binvert

Conclusion

• We can build an ALU to support the MIPS instruction set

– key idea: use multiplexor to select the output we want

– we can efficiently perform subtraction using two’s complement

– we can replicate a 1-bit ALU to produce a 32-bit ALU

• Important points about hardware

– all of the gates are always working

– the speed of a gate is affected by the number of inputs to the gate

– the speed of a circuit is affected by the number of gates in series(on the “critical path” or the “deepest level of logic”)

• Our primary focus: comprehension, however,– Clever changes to organization can improve performance

(similar to using better algorithms in software)– we’ll look at two examples for addition and multiplication

• Is a 32-bit ALU as fast as a 1-bit ALU?• Is there more than one way to do addition?

– two extremes: ripple carry and sum-of-products

Can you see the ripple? How could you get rid of it?

c1 = b0c0 + a0c0 + a0b0

c2 = b1c1 + a1c1 + a1b1 c2 =

c3 = b2c2 + a2c2 + a2b2 c3 =

c4 = b3c3 + a3c3 + a3b3 c4 =

Not feasible! Why?

Problem: ripple carry adder is slow

Appendix: B.6

• An approach in-between our two extremes• Motivation:

– If we didn't know the value of carry-in, what could we do?– When would we always generate a carry? gi = ai bi

– When would we propagate the carry? pi = ai + bi

• Did we get rid of the ripple?

c1 = g0 + p0c0

c2 = g1 + p1c1 c2 =

c3 = g2 + p2c2 c3 =

c4 = g3 + p3c3 c4 =

Feasible! Why?

Carry-lookahead adder

• How about constructing a 16-bit adder in CLA way?

– Can’t build a 16 bit adder this way... (too big)

• Could use ripple carry of 4-bit CLA adders

• Better: use the CLA principle again!

Use principle to build bigger adders

CarryIn

Result0--3

CarryIn

Result4--7

CarryIn

Result8--11

CarryIn

CarryOut

Result12--15

CarryIn

pi + 1gi + 1

ci + 1

ci + 2

ci + 3

ci + 4

pi + 2gi + 2

pi + 3gi + 3

a0b0a1b1a2b2a3b3

a4b4a5b5a6b6a7b7

a8b8a9b9

a10b10a11b11

a12b12a13b13a14b14a15b15

Carry-lookahead unit

P0 = p3 p2 p1 p0 P1 = p7 p6 p5 p4P2 =p11 p10 p9 p8 P3 = p15 p14 p13 p12

G0 = g3+p3g2+p3p2g1+p3p2p1g0G1 = g7+p7g6+p7p6g5+p7p6p5g4G2 = g11+p11g10+p11p10g9+p11p10p9g8G3 = g15+p15g14+p15p14g13+p15p14p13g12

• More complicated than addition

– accomplished via shifting and addition

• More time and more area

• Let's look at 3 versions based on gradeschool algorithm

0010 (multiplicand)

__x_1011 (multiplier)

• Negative numbers: convert and multiply

– there are better techniques, we won’t look at them

Multiplication

Multiplication: Implementation

1. TestMultiplier0

1a. Add multiplicand to product andplace the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions

64-bit ALU

Control test

MultiplierShift right

ProductWrite

MultiplicandShift left

64 bits

32 bits

Second Version

MultiplierShift right

32 bits

64 bits

32 bits

Shift right

Multiplicand

32-bit ALU

Product Control test

1. TestMultiplier0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Multiplier0 = 0Multiplier0 = 1

Yes: 32 repetitions

Final Version

ControltestWrite

32 bits

64 bits

Shift rightProduct

Multiplicand

32-bit ALU

1. TestProduct0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

32nd repetition?

Product0 = 0Product0 = 1

Yes: 32 repetitions

Divide: Paper & Pencil

1001 Quotient

Divisor 1000 1001010 Dividend–1000 10

101 -0000

1010 –1000 10 Remainder (or Modulo result)

See how big a number can be subtracted, creating quotient bit on each step

Binary => 1 * divisor or 0 * divisor

3 versions of divide, successive refinement

DIVIDE HARDWARE Version 1

• 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg

Remainder

Quotient

Divisor

64-bit ALU

Shift Right

Shift Left

WriteControl

32 bits

64 bits

2b. Restore the original value by adding the Divisor register to the Remainder register, &place the sum in the Remainder register. Alsoshift the Quotient register to the left, setting the new least significant bit to 0.

Divide Algorithm Version 1

•Takes n+1 steps for n-bit Quotient & Rem.

Remainder Quotient Divisor

0000 0111 0000 0010 0000

Test Remainder

Remainder < 0Remainder 0

1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.

2a. Shift the Quotient register to the left setting the new rightmost bit to 1.

3. Shift the Divisor register right1 bit.

Yes: n+1 repetitions (n = 4 here)

Start: Place Dividend in Remainder

n+1repetition?

No: < n+1 repetitions

Divide Algorithm I example (7 / 2)

Remainder Quotient Divisor0000 0111 00000 0010 0000

1: 1110 0111 00000 0010 00002: 0000 0111 00000 0010 00003: 0000 0111 00000 0001 00001: 1111 0111 00000 0001 00002: 0000 0111 00000 0001 00003: 0000 0111 00000 0000 10001: 1111 1111 00000 0000 10002: 0000 0111 00000 0000 10003: 0000 0111 00000 0000 01001: 0000 0011 00000 0000 0100 2: 0000 0011 00001 0000 0100 3: 0000 0011 00001 0000 0010 1: 0000 0001 00001 0000 0010 2: 0000 0001 00011 0000 0010 3: 0000 0001 00011 0000 0010

Answer: Quotient = 3 Remainder = 1

Observations on Divide Version 1

• 1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted

• Instead of shifting divisor to right, shift remainder to left?

• 1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration

Divide Algorithm I example: wasted space

Remainder Quotient Divisor0000 0111 00000 0010 0000

1: 1110 0111 00000 0010 00002: 0000 0111 00000 0010 00003: 0000 0111 00000 0001 00001: 1111 0111 00000 0001 00002: 0000 0111 00000 0001 00003: 0000 0111 00000 0000 10001: 1111 1111 00000 0000 10002: 0000 0111 00000 0000 10003: 0000 0111 00000 0000 01001: 0000 0011 00000 0000 0100 2: 0000 0011 00001 0000 0100 3: 0000 0011 00001 0000 0010 1: 0000 0001 00001 0000 0010 2: 0000 0001 00011 0000 0010 3: 0000 0001 00011 0000 0010

Divide: Paper & Pencil

01010 Quotient

Divisor 0001 00001010 Dividend -0000 1

–0001 00

-0000 0001 –0001 00 -0000 Remainder (or Modulo result)

– Notice that there is no way to get a 1 in leading digit!(this would be an overflow, since quotient would haven+1 bits)

• 32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg

Remainder

Quotient

Divisor

32-bit ALU

Shift Left

WriteControl

32 bits

64 bits

Shift Left

Divide Algorithm Version 2Remainder Quotient Divisor

0000 0111 0000 0010

3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0.

Test Remainder

2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.

3a. Shift the Quotient register to the left setting the new rightmost bit to 1.

1. Shift the Remainder register left 1 bit.

Yes: n repetitions (n = 4 here)

nthrepetition?

No: < n repetitions

• Eliminate Quotient register by combining with Remainder as shifted left

– Start by shifting the Remainder left as before.

– Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half

– The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many.

– Thus the final correction step must shift back only the remainder in the left half of the register

• 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg)

Remainder (Quotient)

Divisor

32-bit ALU

WriteControl

32 bits

64 bits

Shift Left“HI” “LO”

Divide Algorithm Version 3

Remainder Divisor

0000 0111 0010

3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0.

Test Remainder

2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.

3a. Shift the Remainder register to the left setting the new rightmost bit to 1.

1. Shift the Remainder register left 1 bit.

Done. Shift left half of Remainder right 1 bit.

Yes: n repetitions (n = 4 here)

nthrepetition?

No: < n repetitions

• Same Hardware as Multiply: just need ALU to add or subtract, and 64-bit register to shift left or shift right

• Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide

• Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary

– Note: Dividend and Remainder must have same sign

– Note: Quotient negated if Divisor sign & Dividend sign disagreee.g., –7 ÷ 2 = –3, remainder = –1

– What about? –7 ÷ 2 = –4, remainder = +1

• Possible for quotient to be too large: if divide 64-bit integer by 1, quotient is 64 bits (“called saturation”)

Floating Point (a brief look)

• We need a way to represent

– numbers with fractions, e.g., 3.1416

– very small numbers, e.g., .000000001

– very large numbers, e.g., 3.15576 109

• Representation:

– sign, exponent, significand: (–1)sign × significand ×2exponent

– more bits for significand gives more accuracy

– more bits for exponent increases range

• IEEE 754 floating point standard:

– single precision: 8 bit exponent, 23 bit significand

– double precision: 11 bit exponent, 52 bit significand

Recall Scientific Notation

6.02 x 10 1.673 x 1023 -24

exponent

radix (base)Mantissa

decimal point

Sign, magnitude

IEEE F.P. ± 1.M x 2e - 127

• Issues:

– Arithmetic (+, -, *, / )

– Representation, Normal form

– Range and Precision

– Rounding

– Exceptions (e.g., divide by zero, overflow, underflow)

– Errors

– Properties ( negation, inversion, if A B then A - B 0 )

Floating-Point ArithmeticRepresentation of floating point numbers in IEEE 754 standard:

single precision1 8 23

exponent:excess 127binary integer

mantissa:sign + magnitude, normalizedbinary significand w/ hiddeninteger bit: 1.M

actual exponent ise = E - 127

N = (-1) 2 (1.M)S E-127

0 < E < 255 (E can not be 0 or 255)

0 = 0 00000000 0 . . . 0 -1.5 = 1 01111111 10 . . . 0

Magnitude of numbers that can be represented is in the range:

(1.0) to 2127

(2 - 2-23 )

which is approximately:

1.8 x 10-38

to 3.40 x 10 38

(1). E can not be 00000000 or 11111111 (reserved)(2). integer comparison valid on IEEE Fl.Pt. numbers of same sign!)

IEEE 754 floating-point standard

• Leading “1” bit of significand is implicit

• Exponent is “biased” to make sorting easier– all 0s is smallest exponent all 1s is largest– bias of 127 for single precision and 1023 for double precision– summary: (–1)sign significand) 2exponent – bias

• Example:

– decimal: -.75 = -3/4 = -3/22

– binary: -.11 = -1.1 x 2-1

– floating point: exponent = 126 = 01111110

– IEEE single precision: 10111111010000000000000000000000

IEEE 754 encoding of floating-point numbers

Single precision Double precision

Object represented

Exponent Fraction Exponent Fraction

0 0 0 0 0

0 Nonzero 0 Nonzero Denomalized number

1-254 Anything 1-2046 Anything Floating-point number

255 0 2047 0 Infinity

255 Nonzero 2047 Nonzero NaN (Not a Number)

Floating Point Complexities

• Operations are somewhat more complicated (see text)

• In addition to overflow we can have “underflow”

• Accuracy can be a big problem

– IEEE 754 keeps two extra bits, guard and round

– four rounding modes

– positive divided by zero yields “infinity”

– zero divide by zero yields “not a number”

– other complexities

• Implementing the standard can be tricky

• Not using the standard can be even worse

– see text for description of 80x86 and Pentium bug!

Floating-Point Addition

• Use , assume four decimal digits of significand and two decimal digits of exponent

• Step 1. Align number for smaller exponent

• Step 2. Significand addition

• Step 3. Normalized scientific notation (overflow or underflow check)

• Step 4. Round the number

015.10

11 10610.110999.9 tenten

111 10016.01001610.010610.1 tententen

21 100015.110015.10 tenten

22 10002.1100015.1 tenten

Flow Diagram of Floating –Point Addition

1. Compare the exponents of the two numbers.Shift the smaller number to the right until itsexponent would match the larger exponent

2. Add the significands

3. Normalize the sum, either shifting right andincrementing the exponent or shifting left

and decrementing the exponent

Overflow orUnderflow?

Exception

4. Round the siginificand to the appropriatenumber of bits

Still normalized?

Block Diagram of Floating-Point Addition

Sign Exponent Fraction Sign Exponent Fraction

Small ALU

Sign Exponent Fraction

Exponentdifference

0 1 0 1

Big ALU

Shift right

Shift left or rightIncrement ordecrement

Rounding hardware

Control

Floating-Point Multiplication (I)

• Use , assume four decimal digits of significand and two decimal digits of exponent

• Step 1. Adding exponent together, and subtract the bias from the sum:

• Step 2. Multiplication on significands:

10212000

510 10200.910110.1 tenten

)1275(132127259127)1275()12710(Exponent New

510212.10212000.10Product ten

Floating-Point Multiplication (II)

• Step 3. Normalized scientific notation (overflow or underflow check)

• Step 4. Round the number

• Step 5. Sign determination

65 100212.110212.10 tenten

66 10021.1100212.1 tenten

610021.1 ten

Flow Diagram of Floating –Point Multiplication

1. Add the biased exponents of the twonumbers, subtracting the bias from the sum

to get the biased exponent

2. Multiply the significands

3. Normalize the product if necessary, shiftingit right and incrementing the exponent

Overflow orUnderflow?

Exception

4. Round the siginificand to the appropriatenumber of bits

Still normalized?

5. Set the sign of the product to positive if thesigns of the original operands are the same;

if they differ make the sign negative

Floating-Point Instructions in MIPS

Name Example Comments

32 floating-point register

$f0, $f1, $f2, …, $f31 MIPS floating-point registers are used in pairs for double precision numbers.

230 memory wordsMemory[0], Memory[4], …, Memory[4294967292]

Accessed only by data transfer instructions. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures, such as arrays, and spilled register, such as those saved on procedure calls.

Category Instruction Example Meaning Comments

Arithmetic

FP add single add.s $f2,$f4,$f6 $f2 = $f4 + $f6 FP add (single precision)

FP subtract single sub.s $f2,$f4,$f6 $f2 = $f4 - $f6 FP subtract (single precision)

FP multiply single mul.s $f2,$f4,$f6 $f2 = $f4 × $f6 FP multiply (single precision)

FP divide single div.s $f2,$f4,$f6 $f2 = $f4 / $f6 FP divide (single precision)

FP add double add.d $f2,$f4,$f6 $f2 = $f4 + $f6 FP add (double precision)

FP subtract double sub.d $f2,$f4,$f6 $f2 = $f4 - $f6 FP subtract (double precision)

FP multiply double mul.d $f2,$f4,$f6 $f2 = $f4 × $f6 FP multiply (double precision)

FP divide double div.d $f2,$f4,$f6 $f2 = $f4 / $f6 FP divide (double precision)

Data transferload word copr. 1 lwc1 $f1,100($s2) $f1 = Memory[$s2+100] 32-bit data to FP register

store word copr. 1 swc1 $f1,100($s2) Memory[$s2+100] = $f1 32-bit data to memory

Conditional branch

branch on FP true bc1t 25 if(cond == 1) go to PC+4+100 PC-relative branch if FP cond.

branch on FP false bc1f 25 if(cond == 0) go to PC+4+100 PC-relative branch if not cond.

FP compare single (eq,ne,lt,le,gt,ge)

c.lt.s $f2,$f4if($f2<$f4) cond = 1;else cond = 0;

FP compare less than single precision

FP compare double (eq,ne,lt,le,gt,ge)

c.lt.d $f2,$f4if($f2<$f4) cond = 1;else cond = 0;

FP compare less than double precision

MIPS floating-point operands

MIPS floating-point assembly language

MIPS Floating-Point Architecture

Name Format Example Comments

add.s R 17 16 6 4 2 0 add.s $f2,$f4,$f6

sub.s R 17 16 6 4 2 1 sub.s $f2,$f4,$f6

mul.s R 17 16 6 4 2 2 mul.s $f2,$f4,$f6

div.s R 17 16 6 4 2 3 div.s $f2,$f4,$f6

add.d R 17 17 6 4 2 0 add.d $f2,$f4,$f6

sub.d R 17 17 6 4 2 1 sub.d $f2,$f4,$f6

mul.d R 17 17 6 4 2 2 mul.d $f2,$f4,$f6

div.d R 17 17 6 4 2 3 div.d $f2,$f4,$f6

lwc1 I 49 20 2 100 lwc1 $f1,100($s2)

swc1 I 57 20 2 100 swc1 $f1,100($s2)

bc1t I 17 8 1 25 bc1t 25

bc1f I 17 8 0 25 bc1f 25

c.lt.s R 17 16 4 2 0 60 c.lt.s $f2,$f4

c.lt.d R 17 17 4 2 0 60 c.lt.d $f2,$f4

Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits

Floating-Point C Program Compiling

• Convert a temperature in Fahrenheit to Celsius

C code: float f2c (float fahr){ return ((5.0/9.0)*(fahr-32.0));}

MIPS ‘code’: f2c: lwc1 $f16, const5($gp)lwc1 $f18, const9($gp) div.s $f16, $f16, $f18 lwc1 $f18, const32($gp) sub.s $f18, $f12, $f18mul.s $f0, $f16, $f18jr $ra

Floating-Point C Procedure with Two-Dimensional Matrices (I)

• Perform matrix multiplication of X = X + Y *Z

C code: void mm (double x[][], double y[][], double z[][])

{ int i, j, k; for(i = 0; i != 32; i = i + 1) for(j = 0; j != 32; i = j + 1) for(k = 0; k != 32; i = k + 1)

x[i][j] = x[i][j] + y[i][k] * z[k][j];}

Floating-Point C Procedure with Two-Dimensional Matrices (II)

• MIPS ‘code’: mm:… li $t1, 32 ; loop termination li $s0, 0; i = 0L1: li $s1, 0; j = 0L2: li $s2, 0; k = 0 sll $t2, $s0, 5 addu $t2, $t2, $s1 sll $t2, $t2, 3 ; byte offset of [i][j] addu $t2, $a0, $t2 ; byte address of x[i][j] l.d $f4, 0($t2)L3: sll $t0, $s2, 5 addu $t0, $t0, $s1 sll $t0, $t0, 3 ; byte offset of [k][j] addu $t0, $a2, $t0 ; byte address of z[k][j] l.d $f16, 0($t0) sll $t2, $s0, 5 addu $t0, $t0, $s2 sll $t0, $t0, 3 ; byte offset of [i][k] addu $t0, $a1, $t0 ; byte address of y[i][k] l.d $f18, 0($t0)

mul.d $f16, $f18, $f16 add.d $f4, $f4, $f16 ; f4 = x[i][j] + y[i][k] * z[k][j] addiu $s2, $s2, 1 ; $k = k + 1 bne $s2, $t1, L3 s.d $f4, 0($t2) ; x[i][j] = $f4 addiu $s1, $s1, 1 ; $j = j + 1 bne $s1, $t1, L2 addiu $s0, $s0, 1 ; $i = i + 1 bne $s0, $t1, L1 …

Rounding with Guard Digits

• Add 2.56ten×100 to 2.34ten×102, assuming three significant decimal digits and round to the nearest decimal number

• With guard and round digits

– Shift the smaller number to right to align the exponents, so 2.56ten×100 become 0.0256ten×102

– Guard hold 5 digit, round hold 6 digit

– yield 2.37ten×102

• Without guard and round digits

– yield 2.36ten×102

2.3656

.02560

3400.2

Chapter Four Summary

• Computer arithmetic is constrained by limited precision• Bit patterns have no inherent meaning but standards do exist

– two’s complement– IEEE 754 floating point

• Computer instructions determine “meaning” of the bit patterns• Performance and accuracy are important so there are many

complexities in real machines (i.e., algorithms and implementation).

• We are ready to move on (and implement the processor)

you may want to look back (Section 4.12 is great reading!)

Chapter Three

Documents

Chapter Three: Socialization Chapter Three: Socialization

Chapter Three Experimental Technique CHAPTER THREE

The Individual Entrepreneur Chapter Three(3) Chapter Three(3)

Chapter Three

METEOROLOGY GEL-1370 Chapter Three Chapter Three Air Temperature

CHAPTER THREE

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Chapter Three, Section Three